低功耗宽调谐范围锁相环设计

针对传统锁相环输出频率范围有限、功耗大的缺陷,通过对压控振荡器震荡机理进行理论分析,设计了一款用于时钟发生器的低功耗、宽调谐范围、低相位噪声锁相环。该锁相环采用了新型可编程、低调谐增益、低功耗的环形振荡器,达到了宽频率输出范围、低相位噪声、低功耗的目的,采用SMIC公司0.18um混合信号工艺,用Cadenced的Hspice仿真工具进行仿真,在1.8V电源电压供电情况下获得了50MHz~1.7GHz的频率锁定范围和1.8mW~2.3mW的较低功耗。单边带相位噪声在10KHz频偏处为-104dBc/Hz.。     

2.4GHz低相位噪声CMOS负阻LC压控振荡器设计

为了有效降低工作于射频段的全集成CIVICS负阻LC压控振荡器的相位噪声,介绍了利用电阻电容滤波技术对振荡器相位噪声的优化,并采用Chartered 0.35μm CMOS标准工艺设计了一款全集成CMOS负阻LC压控振荡器,其中心频率为2.4GHz,频率调谐范围达到300MHz,在3.3V电压下工作时,静态电流为12mA,在偏离中心频率600kHz处,仿真得到的相位噪声为-121dBc/Hz.该设计有效地验证了电阻电容滤波技术对相位噪声的优化效果,并为全集成低相位噪声CMOS负阻LC压控振荡器的设计提供了一种参考电路.     

低相位噪声宽带LC压控振荡器设计

基于0.13μm CMOS工艺,设计了一款低相位噪声宽带LC压控振荡器。采用开关电容阵列使VCO在达到宽调谐范围的同时保持了低相位噪声。采用可变容阵列提高了VCO频率调谐曲线的线性度。仿真结果表明,在1.2 V电源电压下,电路功耗为3.6 m W。频率调谐范围4.58 GHz-5.35 GHz,中心频率5 GHz,在偏离中心频率1 MHz处相位噪声为-125d Bc/Hz。     

2．4GHz低相位噪声CMOS负阻LC压控振荡器设计

为了有效降低工作于射频段的全集成CMOS负阻LC压控振荡器的相位噪声．介绍了利用电阻电容滤波技术对振荡器相位噪声的优化,并采用Chartered 0．35μm CMOS标准工艺设计了一款全集成CMOS负阻LC压控振荡器,其中心频率为2.4GHz,频率调谐范围达到300MHz,在3．3V电压下工作时,静态电流为12mA,在偏离中心频率600kHz处,仿真得到的相位噪声为-121dBc／Hz。该设计有效地验证了电阻电容滤波技术对相位噪声的优化效果,并为全集成低相位噪声CMOS负阻LC压控振荡器的设计提供了一种参考电路。     

一种用于GPS波段的低相噪VCO设计

设计了一种工作频率为1.8 GHz的低相噪频率可调的LC压控振荡器电路。该压控振荡器采用AMOS管作为变容二极管,提高了频率的调谐范围。为了降低电路的相位噪声,设计中采用了PMOS顶部偏置电路代替底部的NMOS偏置电路,并在电路中串联了一个大电容以滤除电路中的高频噪声。仿真测试结果表明,该电路在1 MHz频偏时其相位噪声为-116.5 dBc/Hz。     

低相位噪声低功耗LC压控振荡器的设计

在分析压控振荡器相位噪声的基础上,通过采用尾电流整形滤波技术设计了一种低相位噪声低功耗差分LC压控振荡器.电路设计采用TSMC 0.18um 1P6M CMOS RF工艺,利用Cadence软件中的SpectreRF工具对电路进行了仿真,结果显示,在电源电压VDD=1.8V时,其中心频率为1.8GHz,频率的变化范围为1.43～1.82 GHz,相位噪声为-121dBc/Hz@600kHz.静态功耗仅为2.5mW(1.8V×1.39mA).     

12管低相噪CMOS环形振荡器

提出了一种12管宽线性调谐范围低噪声低功耗的环形振荡器结构。电路设计采用0.18μm的标准CMOS工艺,电源电压为1.8V。SpectreRF仿真结果显示该环形振荡器在27.17MHz到2.062GHz的宽调谐范围内具有良好的线性度。在频率为900MHz、偏移频率为600kHz时,该环形振荡器的相位噪声为-111.1dBc/Hz,功耗为38mW。通过SpectreRF仿真与目前流行的环形振荡器进行比较,本文提出的环形振荡器结构简单、性能优越。     

移动数字电视调谐器中的LC VCO设计

采用TSMC0.13μm CMOS工艺,设计了应用于移动数字电视调谐芯片的宽带VCO。能覆盖UHF和L频段的频率综合器只使用了一个VCO,从而使得芯片的面积和功耗得以减小。为了得到较低的相位噪声并且在宽的调谐范围内输出电压幅度恒定,移除了交叉耦合VCO的尾电流源采用直接电压偏置。VCO电源电压为2V,调谐范围为2.56G Hz-3.84G Hz,仿真结果表明在2.56G Hz和3.84G Hz频偏100K Hz时相位噪声分别为-105dBc/Hz和-95dBc/Hz,整个调谐范围内输出电压峰峰值变化8%,直流功耗15mW。     

可重构振荡器与双频滤波器的协同设计

实现了一种可重构振荡器与双频率滤波器的协同设计模块。振荡器通过开关二极管的通断来实现频率的可重构,工作频率分别为1.1 GHz和2.0 GHz。与双频滤波器协同设计后,振荡器在两个频率上频偏1 MHz的相位噪声分别从-109.1 dBc/Hz和-112.9 dBc/Hz改善为-125.6 dBc/Hz和-127.9 dBc/Hz,二次谐波抑制分别由协同设计之前的-25 dB和-10 dB改善为-44 dB和-55 dB。     

差分LC压控振荡器相位噪声和功耗的优化

基于0.18um射频CMOS工艺,提出三种LC压控振荡器相位噪声和功耗的优化方法.主要思想是:一,通过精心设计,使得PMOS和NMOS差分晶体管对的跨导相等,从而取得对称的输出电压;二,采用偏置晶体管的噪声滤除技术,进一步降低相位噪声;三,确保差分晶体管对的工作区域始终在饱和区和三极管区的边界上,从而实现相位噪声和功耗的最优化.仿真结果证明,在中心频率为2GHz、频率调谐范围为12.4%的条件下,得到最优化的相位噪声为:-102.6dBc/Hz@100KHz、-121.1dBc/Hz@600KHz,且功耗仅为5.4mW.     

RF MEMS压控振荡器的研制及相位噪声特性研究

利用RF MEMS可变电容作为频率调节元件,制备了中心频率为2 GHz的MEMS VCO器件.RF MEMS可变电容采用凹型结构,其控制极板与电容极板分离,并采用表面微机械工艺制造,在2 GHz时的Q值最高约为38.462.MEMS VCO的测试结果表明,偏离2.007 GHz的载波频率100kHz处的单边带相位噪声为-107 dBc/Hz,此相位噪声性能优于他们与90年代末国外同频率器件.并与采用GaAs超突变结变容二极管的VCO器件进行了比较,说明由于集成了RF MEMS可变电容,使得在RF MEMS可变电容的机械谐振频率近端时,MEMS VCO的相位噪声特性发生了改变.     

An Ultra-Low Power Area Efficient Voltage Controlled Oscillator Based on Tunable Active Inductor for Wireless Applications.

This paper presents a tunable active inductor based ultra-low power, low area voltage-controlled oscillator (VCO) in 90 nm CMOS process. In the designed VCO, the modified topology of the active inductor is employed along with tuning capability. The layoutbased simulation has been performed deeming parasitic resistances and capacitances. The designed VCO yields an oscillation frequency ranging from 1.38 GHz to 3.16 GHz with a tuning range of 78.41%, where the tuning voltage is driven from 0.4 V to −0.2 V. The power dissipation varies from 0.062 mW to 0.177 mW, and the VCO provides a differential output power of 8.34 dBm to 3.94 dBm. The phase noise varies from −71 dBc/Hz to −65.4 dBc/Hz, and the Figure of Merit (FoM) has a value of −143.09 dBc/Hz @ 2.79 GHz frequency. The process corner analysis, temperature swept analysis, and Monte Carlo analysis of the proposed VCO had been carried out for the evaluation of its compatibility for diversified environments. Furthermore, the exclusion of the MOS varactor has condensed total silicon area consumption (10.3 μm × 8.5 μm). Finally, the designed VCO's performance parameters have been compared with mentioned designs where it is demonstrated that the designed VCO outdoes the others in most cases along with outstanding outcomes of low power and low silicon area consumption.     

Design of MMIC oscillators using GaAs 0.2 μm PHEMT technology

We propose a feedback type oscillator and two negative resistance oscillators.These microwave oscillators have been designed in the S band frequency.A relatively symmetric resonator is used in the feedback type oscillator.The first negative resistance oscillator uses a simple lumped element resonator which is substituted by a microstrip resonator in the second oscillator to improve results.The negative resistance oscillator produces 4.207 dBm and 7.124 dBm output power with the lumped element resonator and microstrip resonator respectively,and the feedback type oscillator produces ?10.707 dBm output power.The feedback type oscillator operates at 3 GHz with phase noise levels at-83.30 dBc/Hz and-103.3 dBc/Hz at 100 kHz and 1 MHz offset frequencies respectively.The phase noise levels of the negative resistance oscillator with the lumped element resonator are-94.64 dBc/Hz and-116 dBc/Hz at 100 kHz and 1 MHz offset frequencies respectively,at an oscillation frequency of 3.053 GHz.With the microstrip resonator the phase noise levels are-99.49 dBc/Hz and-119.641 dBc/Hz at 100 kHz and 1 MHz offset frequencies respectively,at an oscillation frequency of 3.072 GHz.The results showed that both the output power and the phase noise of the negative resistance oscillators were better than those of the feedback type oscillator.     

Design of a 4.2–5.4 GHz differential LC VCO using 0.35 μm SiGe BiCMOS technology for IEEE 802.11a applications

In this paper, a 4.2–5.4 GHz, ?Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with AMS 0.35 μm SiGe BiCMOS process that includes high‐speed SiGe Heterojunction Bipolar Transistors (HBTs). According to post‐layout simulation results, phase noise is ?110.7 dBc/Hz at 1 MHz offset from 5.4 GHz carrier frequency and ?113.4 dBc/Hz from 4.2 GHz carrier frequency. A linear, 1200 MHz tuning range is obtained from the simulations, utilizing accumulation‐mode varactors. Phase noise was also found to be relatively low because of taking advantage of differential tuning concept. Output power of the fundamental frequency changes between 4.8 dBm and 5.5 dBm depending on the tuning voltage. Based on the simulation results, the circuit draws 2 mA without buffers and 14.5 mA from 2.5 V supply including buffer circuits leading to a total power dissipation of 36.25 mW. The circuit layout occupies an area of 0.6 mm² on Si substrate, including DC and RF pads. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.     

Realization of a VCO for WLAN applications using 0.35 μm‐siGe BICMOS technology

In this article, a 4.5–5.8 GHz, ?G_m LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with Austria MicroSystems 0.35 μm SiGe BiCMOS process that includes high‐speed SiGe heterojunction bipolar transistors (HBTs). According to measurement results, phase noise is ?102.3 dBc/Hz at 1 MHz offset from 5 GHz carrier frequency. A linear, 1300 MHz tuning range is obtained utilizing accumulation‐mode varactors. Phase noise is relatively low because of the advantage of differential tuning concept. Output power of the fundamental frequency changes between ?1.6 and 0.9 dBm depending on the tuning voltage. Average second and third harmonic levels are ?25 and ?41 dBm, respectively. The circuit draws 14 mA DC current from 3.3 V supply including buffer circuits leading to a total power dissipation of 46.2 mW. The prototype VCO occupies an area of 0.6 mm² on Si substrate, including DC and RF pads. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2008.     

一款低噪声八相位锁相环设计

基于宽频率范围数字系统的需求,在0.13μm工艺下设计了一款宽输出范围、低抖动八相位锁相环。首先通过数学建模优化环路带宽,在系统级减小环路噪声;在振荡器中引入了前馈传输管单元以提高振荡频率并降低振荡器相位噪声;最后利用具有伪静态结构的D触发器来降低鉴相器和分频器的功耗并提高其抗噪声能力。仿真结果表明,VCO输出频率在1.2 GHz时相位噪声为-95dBc/Hz@1MHz,FOM功耗为4.5PJ@2GHz。     

A 10 GHz multiphase LC VCO with a ring capacitive coupling structure

A multiphase LC voltage-controlled oscillator(VCO) with a novel capacitive coupling CL ladder filter structure is proposed in this paper and this 10 GHz eight-phase VCO is applied in clock and data recovery(CDR) circuit for 40 Gb/s optical communications system.Compared with the traditional eight-phase oscillator,this capacitive coupling structure can decrease the number of inductors to half and only of four inductors.The VCO is designed and taped out in TSMC 65 nm CMOS technology.Measurement results show the phase noise is 105.95 dBc/Hz at 1MHz offset from a carrier frequency of 10 GHz.The chip area of VCO is 480 μm×700 μm and the VCO core power dissipation is 4.8 mW with the 1.0 V supply voltage.     

用于无线卫星通信网络系统的抑噪分频频率综合器设计

为改善传统综合器在噪声影响下分频效果差的问题,设计了用于无线卫星通信网络系统的抑噪分频频率综合器。根据抑噪分频频率综合器总体架构,设计压控振荡器,并选用MAOC-114850芯片作为压控振荡器核心芯片,依据LC压控振荡器原理电路,将压控可变电抗元件插入输入频率原件中,控制输入控制电压和振动频率,通过改变电容器的充电速率,使产生的电流源在电压控制之内。选用MB506 直插/DIP8 超高频预分频器芯片作为预分频器的核心芯片,经过多次4分频操作定制数字电路。根据环路滤波器的片上集成设计要求,采用三阶无源环路滤波器,改善电阻与电容间的相位裕度,抑噪制声。增加控制模块,限定压控振荡器的最小振荡频率范围,根据晶振参考频率确定跳频间隔,并将结果保存到分频频率综合器中,由此完成抑噪分频频率综合器设计。实验结果表明,该综合器最高分频效率可达到98%,为无线卫星通信网络系统稳定运行提供保障