正电子发射断层成像系统中数字化多通道时间数字转换研究

利用现场可编程门阵列（FPGA）内部延迟链,对正电子发射断层成像（PET）系统中高精度时间数字转换（TDC）进行研究。采用粗时间和精细时间相结合的方式测量时间,粗时间利用时钟计数器实现,精细时间利用FPGA延迟链实现。测试时间测量的微分非线性和积分非线性,并在双探头PET实验平台上通过时间符合,对系统总体时间分辨进行测试。实验结果表明,TDC时间分辨达79.3ps,微分非线性为-0.2LSB/0.2LSB,积分非线性为-0.2LSB/0.3LSB,双探头PET实验系统总体时间分辨达2.1ns,可满足PET系统对时间测量的要求。     

A high precision time-to-digital converter based on multi-phase clock implemented within Field-Programmable-Gate-Array

In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.     

基于FPGA与GPS的时间测量电路设计与实现

为宇宙射线缪子（μ子）测量实验设计了基于FPGA的高精度时间-数字转换器（TDC），结合TDC测量值与GPS提供的标准时间(UTC)精确记录了粒子事件的时间信息。TDC采用粗计数+细时间测量相结合的方式，用计数器实现动态范围大于1 s的粗时间测量；使用FPGA加法进位延时链构建时间内插完成了细时间测量，并借助Wave-Union与bin-by-bin方法提高时间分辨并改善非线性。实验室测试双边沿TDC的时间分辨为16.68 ps，时间测量精度（RMS）好于45 ps。测量结果表明，该TDC满足脉冲前沿时间甄别要求。     

A TDC-Based System for X-Ray Imaging Detectors

An image acquisition system is presented for use with position sensitive detectors (PSD). The system is based on a high-resolution time-to-digital converter (TDC) and a field programmable gate array (FPGA). The detectors use gas as absorbing medium and two delay lines to identify the coordinates of each detected particle. The TDC translates the time information coming from the delay lines into digital words, from which the particle position coordinates are encoded. The FPGA is responsible for processing each event, controlling the data acquisition and communicating with a personal computer. 256 pixels$times$256 pixels images are stored into an on-board memory. This resolution is increased to 512 pixels$times$512 pixels by using a time multiplexing technique. The maximum data acquisition rate is 1.2 million events per second. X-ray images obtained with the system are shown, which illustrate the overall performance.     

An USB-based time measurement system

<正>In this paper,we report the electronics of a timing measurement system of PTB(portable TDC board), which is a handy tool based on USB interface,customized for high precision time measurements without any crates. The time digitization is based on the High Performance TDC Chip(HPTDC).The real-time compensation for HPTDC outputs and the USB master logic are implemented in an ALTERA's Cyclone FPGA.The architecture design and logic design are described in detail.Test of the system showed a time resolution of 13.3 ps.     

基于FPGA的时间间隔测量设计与实现

本文主要介绍了一种基于FPGA的高精度时间-数字转换器(TDC)。该TDC在设计上采用了粗计数与细时间测量相结合的技术。粗计数通过高性能的二进制计数器实现,细时间测量利用FPGA的快速进位链实现时间内插。为了改善测量分辨,在设计中借助Wave-Union方法对超大码宽进行了分割。为检验TDC的性能,对其进行了多项测试,获得较好的测试结果。该TDC在大于200ms的动态范围内的时间分辨率小于50ps。微分非线性(DNL)的范围为-1~1.5LSB,积分非线性(INL)的范围为-1.5~1.5LSB。该TDC将应用于In-beam PET影像装置中的飞行时间测量。     

基于FPGA的时间测量方法的初步研究

设计了一种基于FPGA的TDC(Time Digital Converter)电路．目的在于研究一种可以在北京谱仪Ⅲ的主漂移室时间信息获取中使用的方案。对使用FPGA进行时间测量的方法进行了讨论,并给出了初步测试结果。     

脉冲电流相位检测与反馈系统设计

大多数环型加速器引出束流方向受冲击磁铁的磁场控制,引出冲击磁铁脉冲电源输出的脉冲励磁电流抖动和漂移过大会降低束流引出效率,主要来源于触发系统、闸流管、环境温度变化等[1]。国内抑制引出脉冲电源输出电流相位偏移的相位检测及反馈系统尚属空白。针对中国散裂中子源(CSNS)快循环同步加速器(RCS)引出脉冲电源的需求,设计一种TDC芯片+FPGA结构的输出脉冲电流相位检测及反馈系统,通过研究TDC芯片和FPGA间的数据传输方式、基于FPGA的串口通信及反馈控制算法,实现电源输出电流相位ps级精度实时检测及偏移量反馈,反馈调整步长5 ns,为脉冲电流高精度相位检测与锁定提供了新方法。     

A 250-ps time-resolution CMOS multihit time-to-digital converterfor nuclear physics experiments

This paper presents a CMOS realization of a time-to-digital converter (TDC) for nuclear physics experiments. An innovative and robust architecture, already used in a previous TDC version with 1 ns of bin size, has been adopted and improved with the aim to achieve a 500-ps bin size. The TDC has eight input channels plus a common channel. It can store up to 32 events per channel with a double-hit resolution of 8 ns. It can realize common-start and common-stop operations. It has 4.2 ms of input range with a 125-MHz system clock. The chip uses an asynchronous interpolator system based on a delay-locked line to increase the coarse resolution. It has been fabricated in a double-metal single poly n-well, 1-μm CMOS process with an area of about 77 mm². Measurements show that the TDC has better performance compared to similar devices, especially the time resolution below 250 ps     

A PVT Insensitive Vernier-Based Time-to-Digital Converter With Extended Input Range and High Accuracy

A monolithic Vernier-based time-to-digital converter (TDC) with 37.5 ps time resolution and theoretically unlimited input range has been integrated in TSMC 0.35-mum standard 2P4M CMOS technology. Since the proposed circuit utilizes a single-stage Vernier delay line (VDL) for both coarse and fine measurements, no other interpolation circuit is required. The operation frequencies of the single-stage Vernier delay line are stabilized against process, voltage and temperature (PVT) variations by dual phase-locked loops. The proposed TDC successfully eliminates the element mismatch, input range limitation, external bias adjustment and complicated calibration problems. The measured differential nonlinearity is plusmn0.2 LSB, and the measured integral nonlinearity is plusmn0.35 LSB. The power consumption is 150 mW at 100 k samples/s full conversion speed, and the chip size is as small as 0.222 mm². All the packaged chips were tested to be fully functional over -40degC to 100degC ambient temperature range and 3.0 V to 3.9 V supply voltage range with extremely low resolution variations     

64通道100Ps时间-数字变换模块的研制

兰州重离子加速器冷却储存环外靶实验终端的多丝漂移室通过测量带电粒子的漂移时间得到径迹信息.本文介绍的64通道高精度时间-数字变换模块,采用高密度的连接器和多通道的时间-数字变换芯片HPTDC,模块的数据通过PXI总线传输到计算机,时间精度可达100 ps.     

两个不同原理的延时功能NIM插件的研制

介绍了两套不同原理的延时功能NIM插件的设计。总延时量1μs的短延时插件采用它激同步时钟计数和可编程延时器件的设计方案，延时步长小于30ps，晃动小于50ps总延时量10ms的长延时插件采用基于FPGA，对外部100MHz的有源晶振计数的设计方案，延时步长10ns，晃动10ns。     

Simulation of nuclear reactor dynamics equations using reconfigurable computing

This paper describes the application of a multilayer discrete-time cellular neural network (DT-CNN¹) and its hardware implementation on a field programmable gate array (FPGA²) to model and simulate the nuclear reactor dynamics equations. A new computing architecture model based on FPGA and its detailed hardware implementation are proposed for accelerating the solution of nuclear reactor dynamics equations. The proposed FPGA-based reconfigurable computing platform is implemented on a Xilinx FPGA device and is utilized to simulate step and ramp perturbation transients in typical 2D nuclear reactor cores. Properties of the implemented specialized architecture are examined in terms of speed and accuracy against the numerical solution of the nuclear reactor dynamics equations using MATLAB and C programs. Steady state as well as transient simulations, show a very good comparison between the two methods. Also, the validity of the synthesized architecture as a hardware accelerator is demonstrated.     

一种高精度大范围时间测量电路的实现

时间测量有多种方式,其中用电子学方法实现时间的数字化(TDC)技术是一种常用的技术。根据对时间测量不同的需要,对其测量范围和测量的精度有不同的要求。介绍了一种大测量范围高精度时间测量电路的实现,介绍其实现的原理和设计方法,并给出了测量的结果。     

应用于同步加速器时序控制的片上可编程系统的设计

同步加速器对控制信号的时闻约束要求非常严格,时序控制是加速器控制系统中十分重要的环节.在兰州重离子加速器冷却储存环(HIRFL-CSR)控制系统中,时序控制主要采用FPGA+ARM+linux+DSP的体系结构.本文介绍基于FPGA和uClinux操作系统的片上可编程系统(SOPC)的设计,可将目前ARM+LINUX的工作完全集成在FPGA内实现,省去专用ARM芯片.其最高工作频率可达185 MHz,硬件资源消耗不到4%.片上可编程系统的硬件处理器系统和操作系统都可根据具体需求重新裁剪和配置.SOPC技术在加速器物理以及其他领域有着非常广泛的应用前景.     

一种高精度大范围时间测量电路的实现

在实验核物理中,经常要用到时间测量技术。时间测量有多种方式,其中用电子学方法实现时间的数字化(TDC)技术是一种常用的技术。根据对时间测量不同的需要,对其测量范围和测量的精度有不同的要求,介绍一种大测量范围高精度时间测量电路的实现,其实现的原理和设计方法,并给出了测量的结果。     

高精度数据驱动型TDC在高能物理实验中应用的研究

目前国际国内高能物理方面时间数字转换的发展趋势是使用集成的、高精度、多次击中型TDC,数据驱动型TDC(Data Driven TDC)是其中的热点.研究高性能TDC的具体指标以及改进的方法对高能物理实验中的应用具有指导作用.我们对北京谱仪(BESⅢ)中考虑使用的一种新型高精度TDC进行了测量研究.本文介绍了我们为此建立的测量平台,和对该TDC进行非线性、分辨率、双脉冲分辨等测量的手段和结果,探讨了对其进行甚高精度(24.4 ps)修正的方法,给出了修正的效果.     

基于FPGA状态空间方程解算器的HIRFL-CSR电源控制器设计

兰州重离子加速器冷却储存环(HIRFL-CSR)磁铁电源控制系统迫切需要提高性能,为实现基于现代控制理论的复杂控制算法,设计了ARM+FPGA结构的数字电源控制器。在FPGA中,设计了全新的硬件状态空间方程解算器,对电源进行实时、高速的状态反馈控制。结果证明,控制器可很好地实现最优观测状态反馈闭环控制,且其动态响应速度、稳态精度、抗干扰性及鲁棒性均有很大的提高。     

Printed Low Velocity Delay Lines for Cathode Readout of Proportional Chambers

A new type of flat delay line was developed which has a low propagation velocity and very good delay to rise time ratio. It can be constructed by printed circuit techniques without crossovers. The magnetic loops of a shifted periodic structure yield high inductance per unit length. Geometric scaling factors are shown. This line, forming the cathode plane of a proportional chamber, allows simultaneously, a satisfactory induced signal and the readout of the second coordinate by time delay without disturbing the electric field configuration around the anode. Optimization of position resolution vs. noise is discussed. Experimental results are shown. Other properties of such delay lines are discussed.     

CAMAC四路时间—数字变换器

一、引言在实验技术中,时间-数字变换法出现的较早,也已在核物理实验中有所应用。近10多年来,随着CAMAC和漂移室的出现,时间-数字变换法又得到了新的发展。现在已逐渐应用到其他领域。根据我们的实际需要,研制了一种高分辨的时间-数字变换器。