一种低开销加固锁存器的设计

针对单粒子翻转问题,设计了一种低开销的加固锁存器。在输出级使用钟控C单元,以屏蔽锁存器内部节点的瞬态故障;在输出节点所在的反馈环上使用C单元,屏蔽输出节点上瞬态故障对电路的影响;采用了从输入节点到输出节点的高速通路设计,延迟开销大幅降低。HSPICE仿真结果表明,相比于FERST,SEUI,HLR,Iso-DICE锁存器,该锁存器的面积平均下降23.20%,延迟平均下降55.14%,功耗平均下降42.62%。PVT分析表明,该锁存器的性能参数受PVT变化的影响很小,性能稳定。     

32×32位三端口寄存器堆的加固设计

为了克服集成电路在辐射环境下所受的影响,在SMIC0．18μm工艺下,设计一款应用于LEON3处理器核中的加固的32X32位三端口寄存器堆．存储单元内部采用改进的双向互锁存储单元（DICE）N,外围组合电路采用C-element结构．电路模拟结果表明,室温条件下,工作电压为1．8V,寄存器堆工作在200MHz时,能够实现两读一写的功能,并能同时消除单粒子翻转（SEu）和单粒子瞬态（sET）效应．与汉明码加固方式相比,该方法具有较高的抗辐射能力和较快的速度．     

Low-power pulsed hybrid flip-flop based on a C-element

This paper presents a new flip-flop design featuring implicit pulse-triggered structure in which a dynamic front-end stage and a static back-end one are adopted, thereby, it is considered as a hybrid flip-flop possessing both low-power and high-performance targets. Proposed flip-flop is implemented by a sampling circuit, a C-element for rise and fall paths, and a keeper stage. Simulation results in 45 nm CMOS technology with a 1 V supply voltage demonstrate that 27.8% and 16.9% reductions in terms of power consumption as compared to all other reported flip-flop designs in 25% and 50% data activities, respectively. Moreover, utilizing only four clocked transistors along with transition condition technique make proposed design fast and power-efficient in all activity factors, and exhibiting 5% enhancement in speed. Hence, other exploitable advantage of presented design is power-delay-product (PDP_DQ) index whose improvement ranges from 16.7% to 56%. It is also indicated that presented scheme having negative setup time near zero and considrable hold time contains only 17 transistors severely affecting layout area efficiency being by as much as 12%. More importantly, Monte-Carlo simulations confirm proposed topology gains substantial variation tolerance in power dissipation and PDP_DQ metrics.     

设计和表征一个65nm抗辐射标准单元库

提出了一个基于商用65nm工艺在晶体管级设计抗辐射数字标准单元库的方法。因为当C单元的两个输入是不同的逻辑值时输出会进入高阻模式,并保持输出逻辑电平不变,而当输入端有相同的逻辑值时,C单元的功能就像一个反相器的特性。因此它有把因为辐射粒子引起的单粒子翻转（SEU）效应或单粒子传输（SET）效应所产生的毛刺滤除掉的能力。在这个标准单元库中包含了在晶体管级使用C单元设计了抗辐射的触发器,以便于芯片设计者可以使用这个库来设计具有更高抗辐射能力和减小面积、功耗和延迟的芯片。在最后为了能表征标准单元在硅片上的延迟特性,一个基于环形振荡器的芯片结构用来测量每个单元的延迟,以及验证抗辐射能力。延迟测量结果跟版图后仿真结果偏差在10％以内。     

基于 C 单元的抗干扰低功耗双边沿触发器

快速增长的功耗是 VLSI 设计中的重要问题,特别是输入信号中存在毛刺,双边沿触发器的功耗将会显著增大。 为了有 效降低功耗,提出了一种基于 C 单元的抗干扰低功耗双边沿触发器 AILP-DET,结构采用快速的 C 单元,不仅能够阻塞输入信号 存在的毛刺,阻止触发器内部冗余跳变的发生,降低晶体管的充放电频率;而且增加了上拉-下拉路径,降低了其延迟。 相比现 有的双边沿触发器,AILP-DET 只在时钟边沿采样,有效降低了功耗。 通过 HSPICE 仿真,与 10 种双边沿触发器相比较, AILP-DET 仅仅增加了 7. 58%的延迟开销,无输入毛刺情况下总功耗平均降低了 261. 28%,有输入毛刺情况下总功耗平均降低了 46. 97%。 详尽的电压温度波动分析表明,该双边沿触发器对电压、温度等波动不敏感。     

基于C单元反馈回路的容SEU锁存器设计

随着电子技术的不断发展,集成电路的特征尺寸不断缩小,导致电路对宇宙高能粒子引发的单粒子翻转愈发敏感。提出了一种对单粒子翻转完全免疫的抗辐射加固锁存器。该锁存器利用具有过滤功能的C单元构建反馈回路,并在锁存器末端使用钟控C单元来阻塞传播至输出端的软错误。HSPICE仿真结果显示,在与TMR锁存器同等可靠性的情况下,该锁存器面积下降50%,延迟下降92%,功耗下降47%,功耗延迟积下降96%。     

一个基于C单元双重冗余的65纳米工艺抗辐射触发器

A radiation-hardened flip-flop is proposed to mitigate the single event upset(SEU) effect. Immunity was achieved through the use of C-elements and redundant storage elements. It takes advantage of the property of a C-element in which it enters a high impedance mode when its inputs are of different logic values. Redundant storage nodes are then used to drive the C-elements so that a single upset pulse in any storage will be prevented from altering the state of the output of the flip-flop. The flip-flop was implemented using 48 transistors and occupied an area of 30.78 μm2, using 65 nm CMOS process. It consumed 22.6% fewer transistors as compared to the traditional SEU resilient TMR flip-flop.     

Time redundancy and gate sizing soft error-tolerant based adder design

In this paper, we propose an efficient and promising soft error tolerance approach for arithmetic circuits with high performance and low area overhead. The technique is applied for designing soft error tolerant adders and is based on the use of a fault tolerant C-element connecting a given adder output to one input of the C-element while connecting a delayed version of that output to the second input. It exploits the variability of the delay of the adder output bits, in which the most significant bits (MSBs) have longer delay than the least significant bits (LSBs), by adding larger delay to the LSBs and smaller delay to the MSBs to guarantee full fault tolerance against the largest pulse width of transient error (soft error) for the available technology with minimum impact on performance. To guarantee fault protections for transistors feeding outputs with smaller added delay, the technique utilizes transistor scaling to ensure that the injected fault pulse width is less than the added delay of the second output of the C-element. Simulation results reveal that the proposed technique takes precedence over other techniques in terms of failure rate, area overhead, and delay overhead. The evaluation experiments have been done based on simulations at the transistor level using HSPICE to take care of temporal masking combined with electrical masking. In comparison to TMR, the technique achieves 100% reliability with 31% reduction in area overhead without impacting performance in the case of a 32-bit adder, and 42% reduction in area overhead and 5% reduction in performance overhead in the case of a 64-bit adder. While our proposed technique achieves area reduction of 4.95% and 9.23% in comparison to CE-based DMR and Feedback-based DMR techniques in the case of a 32-bit adder, it achieves area reduction of 19.58% and 23.24% in the case of a 64-bit adder.     

实现R-Port电路的Set-C单元的两种设计

提出了实现r-port电路的set-C单元的两种不同实现方案set-C1与set-C2,给出了r-port电路及set-C1与set-C2的管级电路图,并分析了它们的工作原理.基于0.25 μm标准CMOS无比(ratioless)工艺,给出了r-port电路的仿真图及set-C1与set-C2在上升延迟与平均功耗特性方面的HSPICE对比曲线.仿真结果表明,set-C1、set-C2的最小上升延迟分别为0.154 ns和0.244 ns,比值为1:1.58; set-C1较set-C2节省的最大功耗可达31%.由此得出set-C1较佳的结论.