Modular implementation of efficient self-checking checkers for the Berger code

A technique for designing efficient checkers for conventional Berger code is proposed in this paper. The check bits are derived by partitioning the information bits into two blocks, and then using an addition array to sum the number of 1's in each block. The check bit generator circuit uses a specially designed 4-input 1's counter. Two other types of 1's counters having 2 and 3 inputs are also used to realize checkers for variable length information bits. Several variations of 2-bit adder circuits are used to add the number of 1's. The check bit generator circuit uses gates with fan-in of less than or equal to 4 to simplify implementation in CMOS. The technique achieves significant improvement in gate count as well as speed over existing approaches.     

MOS晶体管的阈值电压不匹配特性

集成电路中器件的匹配性对于模拟电路和数字电路的设计有着很重要的影响,而现在重要的是还缺乏精确的器件匹配的模型。在模拟集成电路设计中,MOS管阈值电压的匹配特性对集成电路尤其是电流Ids的大小有着重要的影响。基于短沟道系列模型,MOS氧化层中的固定电荷和杂质原予服从泊松分布,分析了NMOS和PMOS器件不匹配的物理原因,并验证σVT/VT遵循与1/(?)成比例的结论。     

Thermal Monitoring of Self-Checking Systems

With the increasing power density in integrated systems resulting from scaling down, the occurrence of field failures due to overheating has considerably increased. Faulty operation can be prevented by on-line temperature monitoring. This paper deals with questions of on-line temperature monitoring in safety-critical systems. First the possible temperature sensors are reviewed and basic principles of self-checking systems including such sensors are detailed, then a new temperature sensor cell with extremely good parameters designed especially for DfTT applications is presented. The basic questions of integrating thermal sensors into self-checking systems are also discussed.     

Shorts in self-checking circuits

It has been noted by several authors that the classical stuck-at logical fault model might not be an appropriate representation of certain real failures occurring in integrated circuits. Shorts are an important class of such faults. This article gives a detailed analysis of the effects of shorts in self-checking circuits and proposes techniques for dealing with them. More precisely, we show that, unlike other faults such as stuck-at, stuck-on, and stuck-open—which produce only single errors in the place they occur—shorts can produce double errors on the two shorted lines. In particular, feedback shorts can produce double errors on the two shorted lines. The double error is unidirectional for some feedback shorts and non-unidirectional for some others. Furthermore, in some technologies (e.g., CMOS), non-feedback shorts can also produce double non-unidirectional errors. We also show that unlike stuck-at, stuck-on, and stuck-open faults, redundant shorts can destroy the SFS property. Then we propose several techniques for coping with these problems and we illustrate the results by circuit implementation examples.The present study is given for NMOS and CMOS circuits but we show that it is valid for any other technology.     

Parallel associative combinator evaluation II

A new evaluation model for SK combinator expressions is presented and used as a basis for the design of a novel processor. The resulting machine architecture resembles a dataflow ring, but executions are constrained to be fully lazy. An automatic dynamic load sharing mechanism for a distributed multiprocessor architecture is suggested, and initial simulation results are presented.     

A clustering method to distribute a database on a grid

Clusters and grids of workstations provide available resources for data mining processes. To exploit these resources, new distributed algorithms are necessary, particularly concerning the way to distribute data and to use this partition. We present a clustering algorithm dubbed Progressive Clustering that provides an “intelligent” distribution of data on grids. The usefulness of this algorithm is shown for several distributed datamining tasks.     

Signals,timers, and continuations for multithreaded user‐level protocols

Precise timing and asynchronous I/O are appealing features for many applications. Unix kernels provide such features on a per‐process basis, using signals to communicate asynchronous events to applications. Per‐process signals and timers are grossly inadequate for complex multithreaded applications that require per‐thread signals and timers that operate at finer granularity. To respond to this need, we present a scheme that integrates asynchronous (Unix) signals with user‐level threads, using the ARIADNE system as a platform. This is done with a view towards support for portable, multithreaded, and multiprotocol distributed applications, namely the CLAM (connectionless, lightweight, and multiway) communications library. In the same context, we propose the use of continuations as an efficient mechanism for reducing thread context‐switching and busy‐wait overheads in multithreaded protocols. Our proposal for integrating timers and signal‐handling mechanisms not only solves problems related to race conditions, but also offers an efficient and flexible interface for timing and signalling threads. Copyright © 2006 John Wiley & Sons, Ltd.     

Nd:YAG激光器电光Q开关电路的实验研究

本文报导用于重复频率为40ppsNd:YAG激光器电光Q开关的二种驱动电路的设计和实验研究,并比较了这二种Q开关电路的实验结果.     

基于PVM的并行调试环境

并行软件开发环境的研究已日益成为并行计算和并行处理的重点。本文简介了可移植的消息传递环境ＰＶＭ，讨论了以此为目标的图形监视环境ＸＰＶＭ，阐明ＸＰＶＭ环境与实际需要的ＰＶＭ并行调试环境之间的差距，并在此基础上探讨了并行调试环境开发中的技术难点及其设计要求。     

一类改进的恒频PWM型并联谐振交流器

对传统的并联谐振交流器拓扑结构加以改进，新一类交流器包括两种不同的电路结构，输出电压的调节采用恒频脉宽调制方式。文中通过电路分析、计算机仿真和一台１００ｋＨｚ、２４Ｖ／１００Ｗ变流器的电路实验，以证实改进后变流器所具的优点