无掩模硅图形衬底上3C-SiC的异质外延生长

采用低压化学气相沉积方法在无掩模的硅图形衬底上异质外延生长3C-SiC.硅图形衬底采用光刻和ICP刻蚀得到.图形由平行长条状沟槽和台面组成,其中沟槽宽度为1～10μm不同间隔,沟槽之间距离为1～10μm不同间隔.对于在不同的沟槽和台面尺寸区域3C-SiC的生长进行了详细研究.采用扫描电镜分别观察了不同区域的生长形貌,分析了图形衬底结构上SiC的生长行为.其中合并生长形成的空气隙结构可以释放由Si和SiC晶格失配引起的应力,从而可以用来解决SiC生长中的晶片翘曲问题,进行厚膜生长.XRD结果表明此无掩模硅图形衬底上得到3C-SiC(111)取向生长.     

微机械悬桥法研究氮化硅薄膜力学性能

利用高精密纳米压入仪检测微机械悬桥的载荷-挠度曲线,来研究低应力LPCVD氮化硅薄膜的力学特性。通过大挠度理论分析,得到考虑了衬底变形对挠度有贡献的微桥挠度解析表达式。对于在加卸载过程中表现出完全弹性的微桥,利用最小二乘法对其挠度进行了拟合,从而得到杨氏模量、残余应力和弯曲强度等力学特性参数。低应力LPCVD氮化硅薄膜的研究结果:杨氏模量为(308.4±24.1)GPa,残余应力为(252.9±32.4)MPa,弯曲强度为(6.2±1.3)GPa。     

Effects of Buffer Layer on Hetero-Epi-Growth of SiCGe on 6H-SiC

Growth of SiCGe ternary alloy on 6H-SiC in a conventional hot-wall CVD system was initially studied. SiH4, GeH4 and C3H8 were employed as silicon, germanium and carbon source, respectively, while H2 was employed as the carrier gas. To reduce the heavy lattice mismatch between the film and the substrate, a 3C-SiC buffer layer was inserted between them in a CVD process. Optimizing the growth conditions was discussed. The samples were measured by means of SEM, SAXRD (Small Angle X-Ray Diffraction). It is shown that use of the 3C-SiC buffer layer is an effective way to improve the quality of the ternary alloy.     

SiN介质薄膜内应力的实验研究

研究了低压化学气相淀积Sin(LPCVD)介质薄膜的内应力,采用XP-2型台阶仪测量了SiN介质薄膜的内应力,通过改变薄膜淀积时的工艺参数,观察了反应气体流量比、淀积温度、反应室压力等因素对SiN薄膜内应力的影响.讨论了应力产生的原因以及随工艺条件变化的机理,通过工艺条件的合理选择逐步优化工艺.     

电流增益截止频率为236GHz的InAIN/GaN高频HEMT

研制了高电流增益截止频率(fT)的InAlN/GaN高电子迁移率晶体管(HEMT).采用金属有机化学气相沉积(MOCVD)再生长n+GaN非合金欧姆接触工艺将器件源漏间距缩小至600 nm,降低了源、漏寄生电阻,有利于改善器件的寄生效应;使用低压化学气相沉积(LPCVD)生长SiN作为栅下介质,降低了InAlN/GaN HEMT栅漏电;利用电子束光刻实现了栅长为50 nm的T型栅.此外,还讨论了寄生效应对器件fT的影响.测试结果表明,器件的栅漏电为3.8 μA/mm,饱和电流密度为2.5 A/mm,fT达到236 GHz.延时分析表明,器件的寄生延时为0.13 ps,在总延时中所占的比例为19％,优于合金欧姆接触工艺的结果.     

基于多晶硅填充的TSV工艺制作

硅通孔( TSV)技术用于MEMS器件可实现器件结构的垂直互联,达到减小芯片面积、降低器件功耗等目的。对TSV结构的刻蚀和填充工艺进行了研究,通过优化ICP刻蚀工艺参数获得了端口、中部、底部尺寸平滑减小、深宽比大于20∶1的硅通孔;利用LPCVD技术实现了基于多晶硅的通孔无缝填充;经测试,填充后通孔绝缘电阻达10 GΩ以上,电绝缘性能良好。     

Introduction of atomic H into Si3N4/SiO2/Si stacks

Atomic H generated by a plasma NH3 source at 400 ℃ was demonstrated to passivate dehydrogenated Si3N4/SiO2/Si stacks effectively by bonding with defectsin the Si3N4 film and at the Si-SiO2 interface. A subsequent anneal in N2 after atomic H reintroduction was demonstrated to further improve passivation of the Si-SiO2 interface. Isothermal and isochronal anneals in N2 were carried out in order to determine the optimized annealing conditions.     

Modelling boron diffusion in heavily implanted low-pressure chemical vapor deposited silicon thin films during thermal post-implantation annealing

We have investigated and modelled boron (B) diffusion in heavily implanted silicon (Si) thin films deposited from disilane (Si₂H₆) by low pressure chemical vapor deposition (LPCVD) at low temperatures. A comprehensive one-dimensional two-stream diffusion model adapted to the particular structure of deposited Si films and to the effects of high B concentrations has been developed. This model includes B clustering in grains as well as in grain boundaries. In addition, the effects of Si-films crystallization, during thermal post-implantation annealing, on B diffusion as well as on B clusters formation and dissolution were considered. The effects of clustering, growth of grains, dopant-enhanced grains growth and the driving force for grains growth were coupled with the dopant diffusion coefficients and the process temperature based on thermodynamic concepts. To investigate complex B diffusion in heavily implanted Si films deposited by LPCVD, we have used experimental profiles obtained by secondary ion mass spectroscopy (SIMS) for B implantation with doses of 1 × 10¹⁵ at./cm², 4 × 10¹⁵ at./cm² and 5 × 10¹⁵ at./cm² at an energy of 15 keV. Thermal post-implantation anneals were carried out at relatively low-temperatures (700 °C and 850 °C) for various short-times of 1 min to 15 min. The good adjustment of the simulated profiles with the experimental SIMS profiles allowed the validation of this model. It was found that the simulation well reproduces the experimental SIMS profiles when the growth of grains and immobile B clusters are considered.     

Polycrystalline silicon thin film transistors fabricated in various solid phase crystallized films deposited on glass substrates

In this work, we have characterized various types of polysilicon films, crystallized upon thermal annealing from films deposited by low pressure chemical vapor deposition in the amorphous phase and a mixed phase using silane or in the amorphous phase using disilane. Polysilicon thin film transistors (TFTs) were fabricated, at low processing temperatures, in these three types of films on high strain point Corning Code 1734 and 1735 glass substrates. Double layer films, with the bottom layer deposited in a mixed phase and the top in the amorphous phase, allowed TFT fabrication at a drastically reduced thermal budget; optimum values of thicknesses and deposition rates of the layers are reported for reducing the crystallization time and improving film quality. Optimum deposition conditions for TFT fabrication were also obtained for films deposited using disilane. The grain size distribution for all types of films was shown to be wider for a larger grain size. Fabricated TFTs exhibited field effect electron mobility values in the range of 20 to 50 cm²/V·s, subthreshold swings of about 0.5–1.5 V/dec and threshold voltage values of 2–4 V.     

LPCVD法在GaN上生长Ge薄膜及其特性

本文报道了在GaN/蓝宝石作衬底生长Ge薄膜材料的外延生长及其特性研究。研究了不同外延生长条件。结果表明,使用低压化学气相外延技术在GaN/蓝宝石衬底复合衬底上可以生长Ge薄膜。高分辨X射线衍射谱研究得到了峰位分别位于2θ=27.3°、2θ=45.3°和2θ=52.9°的Ge峰.原子力显微镜研究表明得到的Ge薄膜的表面粗糙度为43.4nm。扫描电子显微镜研究表明生长的Ge/GaN/蓝宝石具有清晰的层界,表面Ge晶粒致密并且分布均匀。Raman谱表明所生长的Ge的TO声子峰位于299.6cm-1,这表明了生长的Ge薄膜具有良好的质量。