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A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16(24)sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip–flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 k Hz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma–delta modulator is applied. When its relative frequency resolution is settled to 10-6, the testing results show that the phase noises are –120.6 d Bc/Hz at 1 MHz and –95.0 d Bc/Hz at 100 k Hz. The chip is2.1 mm2 in UMC 0.18μm CMOS. The power is 36 m W at a 1.8 V supply. 相似文献
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应用于千兆以太网的1-Gb/s 零极点对消CMOS跨阻放大器 总被引:3,自引:2,他引:1
A zero-pole cancellation transimpedance amplifier(TIA)has been realized in 0.35μm RF CMOS technology for Gigabit Ethernet applications.The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration.Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ωfor 1.5 pF photodiode capaci- tance,with a gain-bandwidth product of 3.4 THz·Ω.Even with 2 pF photodiode capacitance,the bandwidth exhibits a decline of only 300 MHz,confirming the mechanism of the zero-pole cancellation configuration.The input resis- tance is 50Ω,and the average input noise current spectral density is 9.7 pA/√ Hz.Testing results shows that the eye diagram at 1 Gb/s is wide open.The chip dissipates 17 mW under a single 3.3 V supply. 相似文献
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本文提出了一种应用于胞外神经记录的全差分带通CMOS前置放大器。这种放大器采用“容性耦合结合容性反馈”式拓扑结构。放大器具有20.4 dB的中带增益,且无直流增益。高频-3 dB截止频率为6.7 KHz,而低频-3 dB截止频率可根据不同频段场电位或动作电位的放大需求作出调整。在3.3 V供电下,放大器的通带设置为0.15 Hz到6.7 KHz(可同时记录本地场电位和神经元峰电位),测得输入参考噪声为8.2 μVrms,功耗仅为23.1 μW。文中也设计了为前置放大器提供偏置电压和偏置电流的带隙参考电路。该原型芯片基于0.35-μm N阱CMOS 2P4M工艺设计与制造,包括前置放大器和偏置电路在内,有源区面积为0.22 mm2。 相似文献
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本文设计并实现了一种应用于超高频射频识别(Ultra High Frequency Radio Frequency , UHF)阅读器的ΔΣFractional-N频率综合器。采用4bit的开关电容阵列实现了885MHz~1020M的16 (2^4)个子带的VCO;7/8双模预分频器使用源极电流耦合逻辑(Source Current Mode Logic, SCML)结构的D触发器及脉冲吞吐电路实现;使用四位三阶的Single-loop 结构实现ΔΣ调制器。频率综合器的频率分辨率为200Hz;参考频率为12.95MHz,仿真结果表明当环路带宽为2π×50k时频率锁定时间小于100us。电路采用UMC 0.18μm 2P6M CMOS工艺制备,芯片面积为1.4mm×1.5mm,测试结果表明电源电压1.8V时功耗20mA,测试总输出相位噪声为:-120.6dBc/Hz @1MHz 和 -95.0dBc/Hz @100kHz。 相似文献
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Silicon photonics is an emerging competitive solution for next-generation scalable data communications in different application areas as high-speed data communication is constrained by electrical interconnects. Optical interconnects based on silicon photonics can be used in intra/inter-chip interconnects, board-to-board interconnects, short-reach communications in datacenters, supercomputers and long-haul optical transmissions. In this paper, we present an overview of recent progress in silicon optoelectronic devices and optoelectronic integrated circuits(OEICs) based on a complementary metal-oxide-semiconductor-compatible process, and focus on our research contributions. The silicon optoelectronic devices and OEICs show good characteristics, which are expected to benefit several application domains, including communication, sensing, computing and nonlinear systems. 相似文献
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