Results in the reconstruction of the pyeloureteral segment using the Anderson-Hynes method

In an introduction the authors take into consideration the term Hydronephrosis and then they reviewed indications for a correction-repair of a pyelo-ureteral segment. There is shortly presented what is to be expected from an "ideal" procedure for a such reconstruction and then the operative technique of Anderson-Hynes method is described. They have operated on 37 patients using this procedure and according to X-ray finding (Degree of dilatation of calices and pyelon) patients were divided into four groups. Of primary importance in the evaluation of end results are: X-ray finding, urine analysis and subjective feeling. According to these criteria an excellent result has been attained in 15 patients, very good in 5, rather good in 8, while in 4 the result was bad; 5 patients were lost to follow-up.     

BER Testing of Communication Interfaces

This paper presents a versatile bit-error-rate (BER) testing scheme to characterize the quality of communication interfaces. Traditionally, the presilicon BER is evaluated using time-consuming software simulations. The stand-alone BER test products for postsilicon evaluation are expensive and do not include channel emulators, which are essential to testing the BER under the presence of noise. For both the design and evaluation phases, we present a scheme for BER testing in field-programmable gate arrays (FPGAs) that consists of a BER tester (BERT) core and a novel additive white Gaussian noise (AWGN) generator core. The maximum output value of our AWGN generator is 53, whereas that of the existing solutions is less than 7. Therefore, our generator can better emulate the tail of a Gaussian distribution, which is suitable for exploring applications at very low BERs. We also present a pipelined structure that exploits the central limit theorem for speedups of four or more. Combining a BERT and an AWGN in FPGAs is orders of magnitude more efficient in cost, volume, and energy over the existing similar-speed stand-alone solutions and has a huge speed advantage over software simulations. We demonstrate the applications of our solution through two case studies.     

GALDS: a complete framework for designing multiclock ASICs and SoCs

A Globally Asynchronous, Locally Synchronous (GALS) system with dynamic voltage and frequency scaling can use the slowest frequency possible to accomplish a task with minimal power consumption. With the mechanism for implementing dynamic voltage scaling at each synchronous domain left up to the designer, our Globally Asynchronous, Locally Dynamic System (GALDS) provides a top-down, system-level means to maximize power reduction in an integrated circuit and facilitate system-on-a-chip (SoC) design. Our solution includes three distinct components: a novel bidirectional asynchronous FIFO to communicate between independently clocked synchronous blocks , an all-digital dynamic clock generator to quickly and glitchlessly switch between frequencies and a digitally controlled oscillator to generate the global fixed frequency clocks required by the all-digital dynamic clock generator. In addition to being capable of reducing power consumption when combined with dynamic voltage scaling, a GALDS design benefits from numerous other advantages such as simplified clock distribution, high performance operation and faster time-to-market through the modular nature of the architecture.     

Problem solving by schizophrenic and schizoaffective patients on the Wisconsin and California Card Sorting Tests.

The performance of patients with schizophrenia or schizoaffective illness was compared with that of age- and education-matched normal controls on the Wisconsin and California Card Sorting Tests (WCST and CCST). On the WCST, both groups of patients achieved fewer than the normal number of categories and made more perseverative responses and errors. On the complete and short versions of the CCST, both patient groups generated, identified, and executed fewer than the normal number of concepts; provided less accurate and less complete verbal explanations for the correct concepts they did generate; and made more verbal and nonverbal perseverative responses than did the controls. There were no differences between patient groups on either test. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

Glycerolipids as selective thrombin inhibitors from the fungus Stereum hirsutum

A dry extract of Stereum hirsutum exhibited a significant inhibitory activity on thrombin (34%). A bioassay oriented fractionation of the extract of Stereum hirsutum has led to the isolation of two active fractions. On the basis of spectroscopic data, chemical reactions, and GC-MS analysis, complex mixtures of diacylglycerophospholipids (DAGPs) and diacylglycerols (DGs) have been isolated and identified. Docking studies suggest that some isolated compounds could bind to the thrombin active site in a similar manner as previously reported phosphonate thrombin inhibitors.     

Kinetics of internal oxidation in Ag-6Sn-2In-1Te-0.2Ni and Ag-6Sn-0.6Cu-1Bi-0.2Ni type alloys

Internal oxidation process was followed in Ag-6Sn-2In-1Te-0.2Ni and Ag-6Sn-0.6Cu-1Bi-0.2Ni alloy types in free air and oxygen at 650 °C and 680 °C. It was found that the Cu and Bi bearing alloy had a higher rates of internal oxidation in all of the tested conditions, whish was due to Bi effect accelerating the internal oxidation. In the early stage of internal oxidation of the Ag-6Sn-2In-1Te-0.2Ni alloy, an inhomogeneous structure revealed, which changed to a homogenous pattern after longer oxidation times. Such a structure was suppressed in the Bi bearing alloy. The applied 6 bar oxygen atmosphere brought on a 5–6 times higher rate of internal oxidation, with a homogenous structure compared to the free air oxidation. In free air after long time oxidation (200 h–250 h), the rate of internal oxidation was found to have almost doubled in both alloys.     

Glycerolipids as Selective Thrombin Inhibitors from the Fungus Stereum Hirsutum

ABSTRACT

A dry extract of Stereum hirsutum exhibited a significant inhibitory activity on thrombin (34%). A bioassay oriented fractionation of the extract of Stereum hirsutum has led to the isolation of two active fractions. On the basis of spectroscopic data, chemical reactions, and GC-MS analysis, complex mixtures of diacylglycerophospholipids (DAGPs) and diacylglycerols (DGs) have been isolated and identified. Docking studies suggest that some isolated compounds could bind to the thrombin active site in a similar manner as previously reported phosphonate thrombin inhibitors.     

A Fault Tolerant Hierarchical Network on Chip Router Architecture

Continuing advances in the processing technology, along with the significant decreases in the feature size of integrated circuits lead to increases in susceptibility to transient errors and permanent faults. Network on Chips (NoCs) have come to address the demands for high bandwidth communication among processing elements. The structural redundancy inherited in NoC-based design can be exploited to improve reliability and compensate for the effects of failures. In this paper, we propose an enhanced fault tolerant microarchitecture with deadlock-free routing for Hierarchical NoCs. The proposed router supplies dynamic Virtual Channel (VC) Allocation, and it employs a high-performance fault tolerant control flow, handling both transient and permanent faults in hierarchical networks without extra retransmission buffer requirements. Experimental results show a significant improvement in reliability as well as decreases in the average latency and energy consumption.     

Oversampled multi-phase time-domain bit-error rate processing for transmitter testing

High speed serial interfaces (HSSI) are continually pushed toward operating at higher speed to meet the demand for higher bandwidth. As a result, the timing constraints for HSSI devices get tighter. Consequently, HSSI devices experience issues such as timing jitter and bit-errors. This paper investigates techniques to speed up HSSI bit-error rate and jitter testing. The proposed oversampling-based transmitter test scheme accelerates transmitter jitter and eye diagram testing by means of a multi-phase bit-error rate test circuit (BERT). The proposed scheme creates parallel BERT elements working in conjunction that are able to digitize the input signal jitter behavior in a multi-phase manner. The more phases we deploy the faster the test is completed. We accurately extract the transmitter jitter in time domain and finish the whole transmitter test within tens of milliseconds, exceeding the current norm of 100 ms.