低压静电场辅助冷冻对竹笋品质的影响

为研究低压静电场辅助冷冻对竹笋冻结特性的影响，以冻结曲线、硬度、水分损失率、水分迁移、冰晶形态和组织微观结构为指标，探究低压静电场辅助冷冻（－35 ℃）和普通冷冻（－35 ℃）条件下竹笋品质的变化规律。结果表明：低压静电场辅助冷冻提高了冻结效率，改变了冰晶形态及分布，减轻了组织微观结构破损程度，改善了解冻汁液流失情况。与静电板间距10、20、30、40 cm处的冷冻竹笋解冻后水分损失率分别为14.16%、12.58%、9.73%、10.44%，显著低于对照组（21.01%）（P＜0.05），硬度分别为461.19、507.48、496.65 g和455.31 g，显著高于对照组（350.70 g）（P＜0.05）。低场核磁共振分析结果表明，在低压静电场辅助冷冻下竹笋解冻后汁液流失减少，扫描电子显微镜观察结果显示，竹笋纤维排列整齐，组织微观结构保持较好。低压静电场辅助冷冻可有效改善竹笋品质，可为利用低压静电场进行果蔬的冷冻贮藏和冷链运输提供参考。     

A Voltage Control Method for a Distributed Line Feeder by means of Multiagent Approach

This paper proposes a method for the coordinated control of power factor by means of a multiagent approach. The proposed multiagent system consists of two types of agent: single feeder agent (F_AG) and bus agent (B_AG). In the proposed system, an F_AG plays as an important role, which decides the power factors of all distributed generators by executing the load flow calculations repeatedly. The voltage control strategies are implemented as the class definition of Java into the system. In order to verify the performance of the proposed method, it has been applied to a typical distribution model system. The simulation results show that the system is able to control very violent fluctuation of the demands and the photovoltaic (PV) generations.     

电压对电刷镀三价铬镀层性能的影响

在45钢表面电刷镀得到三价铬镀层,镀液组成和工艺条件为:Cr2(SO4)36H2O 0.4 mol/L,甲酸铵0.5 mol/L,氨基乙酸0.5 mol/L,H3BO30.6 mol/L,NaH2PO2 H2O 0.3 mol/L,pH=1.5,温度50°C,镀笔移动速率15 cm/s。研究了电压对镀铬层显微结构、表面粗糙度、厚度、显微硬度和耐磨性的影响。随电压增大,镀层厚度增大,显微硬度和耐磨性均先提高后降低。电压为14 V时,镀层的表面平整,粗糙度为2.387μm,显微硬度为602 HV,耐磨性最好。     

巨型水电站孤岛试验期间AVC电压波动的解决

本文首先分析国内典型的AVC的一般配置、控制策略和控制原理,针对巨型水电站孤岛试验期间的AVC控制的复杂工况进行阐述,对出现的AVC电压波动的情况进行分析,并对采用的解决方案进行介绍,为今后类似电站的孤岛运行期间的AVC电压控制提供一些参考建议。     

仪器仪表产品脉冲耐压试验要求和保护器件的选择

仪器仪表产品的脉冲耐压试验是产品型式试验、例行试验中的基本内容。通过对GB4793.1标准的整理,归纳了仪器仪表产品的脉冲耐压试验要求。通过对试验方法和设备特性的梳理,总结了特性参数,并介绍了应对脉冲耐压试验可采取的保护器件的类别及选用方法。     

Assessing students' conceptual understanding using an online three‐tier diagnostic test

When solving a mathematical problem, students who do not have sufficient conceptual understanding may perform poorly and exhibit misconceptions. This study was aimed to examine students' conceptual understanding and significant misconceptions when solving number sense‐related problems. An online three‐tier diagnostic test was administered to 125 fifth‐grade students with varied socio‐economic backgrounds in Hong Kong. Only 14.40% of the students exhibited high performance with high confidence, indicating that these students had a profound conceptual understanding of number sense. In addition, the majority of the students (66.40%) did not demonstrate number sense; these students exhibited several significant misconceptions and could solve the questions only by using a rule‐based method or guessing. Accordingly, most students performed unsatisfactorily on number sense‐related problems. This study is imperative in identifying early predictors and provides information for further compatible interventions in the teaching and learning of number sense in Hong Kong in particular and worldwide in general.     

基于关键路径延时检测的自适应电压缩减技术

为了减小传统的最差情况设计方法引入的电压裕量,提出了一种变化可知的自适应电压缩减(AVS)技术,通过调整电源电压来降低电路功耗.自适应电压缩减技术基于检测关键路径的延时变化,基于此设计了一款预错误原位延时检测电路,可以检测关键路径延时并输出预错误信号,进而控制单元可根据反馈回的预错误信号的个数调整系统电压.本芯片采用SMIC180 nm工艺设计验证,仿真分析表明,采用自适应电压缩减技术后,4个目标验证电路分别节省功耗12.4％,11.3％,10.4％和11.6％.     

Design and performance study of phase‐locked loop using fractional‐order loop filter

The present work reports the realization of an analog fractional‐order phase‐locked loop (FPLL) using a fractional capacitor. The expressions for bandwidth, capture range, and lock range of the FPLL have been derived analytically and then compared with the experimental observations using LM565 IC. It has been observed that bandwidth and capture range can be extended by using FPLL. It has also been found that FPLL can provide faster response and lower phase error at the time of switching compared to its integer‐order counterpart. Copyright © 2014 John Wiley & Sons, Ltd.     

High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (R_on,sp) of 2 mΩ cm², which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.