A survey on nonlinear analog-to-digital converters

This paper presents a survey on Nonlinear Analog-to-Digital converters (ADC). This class of converters is extremely relevant in applications where there is a need for non-uniform quantization characteristic, for example, some specific applications in the areas of light detection, hearing aid, nuclear physics, image acquisition, communication systems, etc. This survey outlines the state-of-the-art Nonlinear ADC topologies, such as, floating point, logarithmic, piecewise linear and oversampled nonlinear converters, and discusses their performance and advantages in terms of their applications.     

混合滤波器组ADC通路失配偏差的校准方法

 针对各采样通路之间的不匹配影响混合滤波器组ADC的重构精度这一问题,本文提出了一种校准混合滤波器组ADC通路失配偏差的模型,该模型将通路间的增益偏差、相位偏差和带宽失配偏差引入到混合滤波器组ADC中.基于此模型,建立根据输出数据求解超定方程组估算失配偏差的方法,给出引入失配偏差的混合滤波器组的结构,推导出其完美重构条件.设计实现了160MHz 12-bit的两通路混合滤波器组ADC系统,实验结果表明,提出的通路失配偏差的校准方法可提高系统的无杂散动态范围(SFDR)23dB.     

Perfect reconstruction of uniform samples from K-th order nonuniform samples

In this paper, we propose a new discrete-time model which relates uniform samples and K-th order nonuniform (KONU) samples. Typically, such situations may occur in practice where the sampling rates of analog-to-digital converters (ADCs) in a cluster of sensors may be different. This paper also outlines a digital signal processing approach to reconstructing uniform samples from the nonuniform samples produced by time interleaving analog-to-digital converters (TI-ADCs) with different sampling rates and time-mismatches.     

高精度模数转换器在压力信号采集系统中的应用

本文设计的压力信号采集系统采用了高精度24位的模数转换器ADS1255.如何使用这种高性能的模数转换器,本文给出了硬件和软件设计方法并作了详细的说明.本文使用的模数转换器硬件精度高,接口简单,通用性强.使用这种高精度模数转换器的压力信号采集系统稳定可靠,已通过了井下试验的测试,满足采集井底压力信号的要求.     

一种适用于中频接收机的具有75dB动态范围的100MHz带通$\Sigma \Delta$调制器

本文介绍了一款适用于中频接收机的四阶开关电容带通$\Sigma \Delta$调制器,采样频率为100MHz。为优化谐振器的性能,文中提出了考虑运算放大器非理想特性后谐振器的传输函数。本文设计的调制器采用0.13-um标准CMOS工艺,在25MHz附近200KHz信号带宽内测得的SNDR和DR分别为68dB和75dB。调制器工作在1.2V电源电压下,总功耗为8.2mW。     

A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented.The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter,which are based on well-designed calibration reference, calibration DAC and comparators.The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.     

一种用于逐次逼近ADC的高能效高线性度开关电容时序

提出了一种用于逐次逼近模数转换器的高能效高线性度开关电容时序。相较于典型的基于V_CM的开关原理,该开关时序可减少37%的开关能量,并具有更高的线性度。该开关时序已应用于1V,10位300kS/s的SAR ADC,并在0.18μm标准CMOS工艺下成功流片。测试结果表明,在1V电源电压下,此SAR ADC的SNDR为55.48dB,SFDR为66.98dB,功耗为2.13μW,品质因数到达14.66fJ/c-s。DNL和INL分别为0.52/-0.47 LSB和0.72/-0.79 LSB,并且与静态非线性模型一致,最大INL出现在 V_FS/4处和3V_FS/4处。     

Design of Pipelined ADC Using Op Amp Sharing Technique

This paper presents a 10-bit 20 MS/s pipelined Analog-to-Digital Converter(ADC)using op amp sharing approach and removing Sample and Hold Amplifier(SHA)or SHA-less technique to reach the goal of low-power consumption.This design was fabricated in TSMC 0.18 μm 1P6M CMOS technology.Measurement results show at supply voltage of 1.8 V,a SFDR of 42.46 dB,a SNDR of 39.45 dB,an ENOB of 6.26,and a THD of 41.82 dB are at 1 MHz sinusoidal signal input.In addition,the DNL and INL are 1.4 LSB and 3.23 LSB respectively.The power consumption is 28.8 mW.The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.     

用于电荷域流水线ADC的1.5位子级电路

针对高速高精度模数转换器的性能依赖于高增益带宽积运放而导致较大功耗的问题,提出了一种基于斗链式电荷器件的电荷域流水线1.5位子级电路．该子级电路使用增强型电荷传输电路来实现电荷传输和余量电荷计算,去除了传统流水线模数转换器中的高性能运放,可大大降低模数转换器的功耗．基于所提出的1.5位子级电路,在0.18μm CMOS工艺条件下,设计了一款10位、250MS/s电荷域流水线模数转换器．测试结果表明,该模数转换器样片在全速采样时对于9.9MHz正弦输入信号转换得到的无杂散动态范围为644dB,信噪失真比为56.9dB,而功耗为45mW．