ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing

To meet both flexibility and performance requirements, particularly when implementing high-end real-time image/video processing algorithms, the paper proposes to combine the application specific instruction-set processor (ASIP) paradigm with the reconfigurable hardware one. As case studies, the design of partially reconfigurable ASIP (r-ASIP) architectures is presented for two classes of algorithms with widespread diffusion in image/video processing: motion estimation and retinex filtering. Design optimizations are addressed at both algorithmic and architectural levels. Special processor concepts used to trade-off performance versus flexibility and to enable new features of post-fabrication configurability are shown. Silicon implementation results are compared to known ASIC, DSP or reconfigurable designs; the proposed r-ASIPs stand for their better performance–flexibility figures in the respective algorithmic class.

Algorithmic and architectural design for real-time and power-efficient Retinex image/video processing

This paper presents novel algorithmic and architectural solutions for real-time and power-efficient enhancement of images and video sequences. A programmable class of Retinex-like filters, based on the separation of the illumination and reflectance components, is proposed. The dynamic range of the input image is controlled by applying a suitable non-linear function to the illumination, while the details are enhanced by processing the reflectance. An innovative spatially recursive rational filter is used to estimate the illumination. Moreover, to improve the visual quality results of two-branch Retinex operators when applied to videos, a novel three-branch technique is proposed which exploits both spatial and temporal filtering. Real-time implementation is obtained by designing an Application Specific Instruction-set Processor (ASIP). Optimizations are addressed at algorithmic and architectural levels. The former involves arithmetic accuracy definition and linearization of non-linear operators; the latter includes customized instruction set, dedicated memory structure, adapted pipeline, bypasses, custom address generator, and special looping structures. The ASIP is synthesized in standard-cells CMOS technology and its performances are compared to known Digital signal processor (DSP) implementations of real-time Retinex filters. As a result of the comparison, the proposed algorithmic/architectural design outperforms state-of-art Retinex-like operators achieving the best trade-off between power consumption, flexibility, and visual quality.

基于二进制插桩的ASIP处理器指令集混合仿真方法

指令集仿真器在ASIP处理器硅前软件开发中发挥着重要的作用,但使用传统仿真方法的指令集仿真器仿真速度较慢.基于二进制插桩,提出了ASIP处理器指令集混合仿真方法,以混合仿真的方式,使基础指令直接运行在宿主机上,仅对扩展指令仿真,从而降低仿真开销,提升仿真速度.实验表明,采用此方法对主流高清音视频解码软件进行仿真的平均速度达到了1058.5MIPS,是采用当前先进的动态二进制翻译仿真方法仿真器速度的34.7倍.     

面向无线局域网安全领域的片上网络多核架构

在计算机系统和通信网络中,安全协议和密码算法用于保护敏感信息,但如何快速计算上述协议和算法成为难题。为此,提出一种面向无线局域网安全领域的片上网络多核架构。该片上网络架构包括4个类MIPS的精简指令集处理器和12个面向安全领域的专用指 令集处理器(ASIP)。每个ASIP中含有一个改进的并行查找表用来加速高级加密标准算法。该架构凭借任务并行能够获得较高的计数器模式密码块链消息完整码协议吞吐率。在SMIC 0.13 μm标准CMOS工艺下,实现该架构需要约308万等效门。实验结果表明,该系统的最大工作频率为84 MHz,能获得787 Mb/s的吞吐率。     

密码处理ASIP中的置换加速

密码处理ASIP是针对密码算法处理的专用微处理器体系结构,结构设计的重点是怎样良好地匹配算法要素和算法结构.置换是对称密码算法中重要的编码环节,在密码处理ASIP结构下加速置换要尽量减少使用非共用硬件,开发处理并行性,适应各种位宽置换的处理要求.通过对分组算法置换特性的深入分析,在提出的密码处理ASIP结构下,构造了加速置换操作的部件结构和互连结构,设计了专用的指令,给出了性能和实现结果,证明置换加速机制高效、低代价、通用性强.     

周期精确ASIP仿真器生成环境的研究

周期精确仿真器是ASIP(专用指令集处理器)开发过程中的关键工具.介绍了一种由体系结构描述语言mtADL驱动的周期精确ASIP仿真器的快速生成环境.mtADL可以简洁精确地描述嵌入式领域最常见的2种微体系结构(简单流水线和Tomasulo动态调度流水线).仿真器生成器mtGEN能够根据mtADL的描述,自动生成周期精确的仿真器.介绍了mtGEN使用的自动生成算法.在实验部分,对5级流水MIPS、3级流水ARM7和动态调度MIPS这三种差异很大的处理器实现了周期精确仿真器自动生成,从而证明了方法的正确性和有效性.     

面向专用指令集处理器设计的软硬件协同验证

为提高专用指令集处理器设计中的验证效率和覆盖率,将专用指令集处理器的寄存器传输级设计验证与汇编器、指令集模拟器等软件开发工具的测试相结合,提出一种软硬件协同验证方法。该方法按照覆盖率要求由软件自动产生测试程序和数据,将利用汇编器产生的机器指令输入到指令集模拟器和硬件仿真工具分别进行软硬件仿真,通过软硬件仿真结果自动比对得出联合验证结果。实践证明,该方法能够有效提高验证效率和覆盖率,缩短验证周期。     

加密专用处理器指令集设计

源码分析技术是一种重要的专用处理器设计方法,用于定位程序运行的瓶颈所在.通过新颖的细粒度源码分析技术,针对加密应用,扩展的开源可扩展处理器OR1K指令集以协处理器的方式和主处理器紧密耦合,可以获得相比传统设计方法更高的效率和更好的性能.实验结果表明,指令扩展后的处理器相比原处理器在增加较少芯片面积消耗的情况下处理效率提高为扩展前的1.78倍.     

一种适用于有线DTV双向传输系统的协议处理单元的设计

设计了一个PPU(Protocol Processing Unit,协议处理单元),实现了有线DTV双向传输系统中多个模块之间通信的协调功能.该PPU采用了ASIP的设计方法,根据模块间具体的通信特点设计了模块专用接口、中断机制和专用指令,提高了硬件资源的利用率,具有很好的功能可扩展性和灵活性.同时设计了精简的汇编代码,仿真结果表明该代码在对模块接口的响应上具有很好的实时性.综合结果表明,PPU能够提供多种吞吐量.