分离栅式快闪存储器擦除性能的工艺优化

随着电子产品的普及,分离栅式快闪存储器作为闪存的一种,由于具有高效的编程速度以及能够完全避免过擦除的能力,无论是在单体还是在嵌入式产品方面都得到了人们更多的关注。随着闪存市场高集成度的发展需求,分离栅式快闪存储器的尺寸也在逐渐地缩小。从结构和工艺优化方面探讨在这一微缩过程中,如何有效提高分离栅式快闪存储器的擦除效率。通过实验发现通过形成非对称性浮栅结构,优化浮栅到擦除栅侧的结构形貌,可以显著改进分离栅式工艺快闪存储器的擦除性能。     

快闪存储器──存储器家族的新成员

磁盘和快闪存储器有一个共同的特点，即整块数据存储。计算机通常采用磁盘存储整块数据，而快闪存储器在数据存储方面更具有优越性。我们研究了快闪存储单元及其工作原理，从中了解到快闪存储器的特性以及与便携式计算机比较的结果。     

快闪存储器—存储器家族的新成员

磁盘和快闪存储器有一个共同的特点，即整块数据存储。计算机通常采用磁盘存储整块数据，而快闪存储器在数据存储方面更具有优越性。我们研究了快闪存储单元及其工作原理，从中了解到快闪存储器的特性以及与便携式计算机比较的结果。     

快闪存储器及其应用

本文评述存储器家庭新成员－快闪存储器的结构原理和特性，研制进展，编程擦除方法以及使用注意事项，提供了快闪存储器的多种应用途径。     

分离栅式快闪存储器抗编程干扰性能的工艺优化

随着电子产品的普及,分离栅式快闪存储器作为闪存的一种,因其具有高效的编程速度以及能够完全避免过擦除的能力,无论是在单体还是嵌入式产品方面都得到了人们更多的关注。但由于快闪存储器产品规则的阵列排列方式,高速的编程能力也带来了容易出现编程干扰的问题,成为了制约其实际应用的关键因素。从工艺优化方面探讨在编程过程中,如何有效提高分离栅式快闪存储器的抗编程干扰性能。通过实验发现通过整合改进工艺流程中调节字线阈值电压的离子注入方式的方法,可以显著改进分离栅式工艺快闪存储器的抗编程干扰性能。     

多电平快闪存储器技术及其未来发展

多电平单元（MLC）快闪存储器是一种新兴的闪存技术,单元面积小,制造成本低,虽然MLC的多项指标都落后于单电平单元（SLC）快闪存储器,但是MLC在架构上取胜于SLC,很多厂商目前都对MLC做了很多的优化和开发,对于MLC传输速度和读写次数的问题已经有了相当多的解决方法,其多项性能逐步可以和SLC芯片相比拟,而且会节省相当多的成本。本文对多电平快闪存储器的单元结构、基本操作、可靠性问题及未来的发展作了详细介绍。     

快闪存储器前途无量

一、全球快闪存储器市场 正当全球半导体市场面临货源短缺而厂商将发展的关注焦点集中到动态存储器上时,快闪存储器(Flash memory)也面临了市场需求殷切所产生短缺的问题。但由于快闪存储器的产品发展技术与特性都与动态存储器有相当大的差异,因此在市场竞争厂商不多的状况下,所引起的关注也就不像动态存储器那样引人注目。     

USB快闪存储器使用全接触

<正> 在移动存储市场中,有一种钢笔大小的USB移动存储器越来越引人注目,那就是USB快闪存储器。目前已经有很多厂家都投入到了USB快闪存储器的开发和生产中去,再加上Flash ROM芯片价格的下降,使得USB快闪存储器的售价一降再降,逐渐为消费者所接受。     

快闪存储器阈值电压分布读取和修正方法

在快闪存储器中,多晶硅浮栅的漏电、存储单元之间的干扰、长期的编程擦除操作都会使存储单元的阈值电压发生漂移,使采用多电平技术的快闪存储器的阈值电压分布规划变得越来越困难。针对这一问题,提出了一种快闪存储器阈值电压分布读取方法,该方法能准确地测量快闪存储器的阈值电压分布,给快闪存储器阈值电压分布规划和编程擦除算法的设计提供参考。     

爱特梅尔嬴得专利诉讼

爱特梅尔(ATMEL)公司（那斯达克ATML）2000年10月17日宣布了美国国际贸易委员会(ITC)编号为337-TA-395的调查结果及最终裁定以及有限驱逐令。美国国际贸易委员会发现：在可擦可编程只读存储器(EPROM)，电可擦可编程只读存储器(EEPROM)，快闪存储器(Flash)以及快闪存储器微处理器等半导体器件以及产品领域中，爱特梅尔公司的编号为4,451,903美国专利是有效的，可执行的。 另外，美国国际贸易委员会宣布了有限驱逐令以禁止“侵权的可擦可编程只读存储器，电可擦可编程只读存储器，快闪存储器以及快闪存储器微处理器等半导体器件以及包含这些器件的电子产品进入美国市场”。ITC进一决定，“根据关税法337(j)条款的规定，在等待总统通知委员会关于驱逐令的最终决定的60天期限内，侵权器件以及包含这些器件的电子产品只有缴纳每件0.78美元后才能够进入美国市场”。     

闪存在嵌入式Linux系统中的应用

在深入分析各种闪存及相关文件系统特点的基础上,针对实际系统中对闪存的不同使用需求,采取不同的应用方案：通过启动加载程序直接读／写,通过Linux系统中的文件系统读／写和跳过文件系统通过底层操作函数读／写,获得了较好的性能和较好的可靠性。对生产过程中的程序代码和数据写入实现了一定程度的自动化,对于类似系统有一定的借鉴意义。     

Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories

Constant-charge-injection programming (CCIP) has been proposed as a way to achieve high-speed multilevel programming in flash memories. In order to achieve high programming throughput in multilevel flash memory, programming method must provide: 1) high-speed cell-programming; 2) high programming efficiency; and 3) highly uniform programming characteristics. Conventional source-side channel-hot-electron injection (SSI) programming realizes both fast cell-programming and high programming efficiency, but the large cell-to-cell variation in programming speed with SSI is a problem. CCIP reduces the characteristic variation of SSI programming and satisfies all of the above requirements. By applying CCIP to 2-bit/cell AG-AND flash memory, the high programming throughput of 10.3 MB/s is obtained with no area penalty. This is 1.8 times faster than the throughput with conventional SSI programming.     

Reliability issues of flash memory cells

Reliability issues for flash electrically erasable programmable read-only memories are reviewed. The reliability of both the source-erase type (ETOX) flash memory and the NAND structure EEPROM are discussed. Disturbs during programming, write/erase endurance, charge loss of both devices are reviewed, and the reliability of the tunnel oxide and the interpoly dielectric are described. It is shown that bipolarity F-N programming/erase, which is used in the NAND EEPROM, improves the charge to breakdown and decreases the stress-induced leakage current     

Ferroelectric memory: on the brink of breaking through

With a memory-cell size comparable to that of a DRAM memory cell and a manufacturing process similar to that of a stacked high-density DRAM, it can be expected that the ferroelectric technology will leverage off DRAMs and leap frog to higher memory densities. Cost analysis projects cost competitiveness with flash memory and EEPROM. Ferroelectric memory technology has been shown to have reliability levels comparable to or better than other reprogrammable nonvolatile semiconductor memories. High levels of radiation hardness make these memories suitable for near and deep-space applications. Many large semiconductor companies have substantial efforts to develop and introduce ferroelectric memories into the market     

一种用于NAND闪存的奇偶位线块编程补偿算法

为改善数据保持干扰和编程干扰对NAND闪存可靠性的影响,提出了一种新的奇偶位线块编程补偿算法。该算法利用编程干扰效应来补偿由数据保持引起的阈值漂移,修复NAND闪存因数据保持产生的误码,提高了NAND闪存的可靠性。将该算法应用于编程擦除次数为3k次的1x-nm MLC NAND闪存。实验结果表明,在数据保持时间为1年的条件下,与传统奇偶交叉编程算法相比,采用该补偿算法的NAND闪存的误码降低了93%;与读串扰恢复算法相比,采用该补偿算法的NAND闪存的误码下降了38%。     

Program load adaptive voltage generator for flash memories

This paper describes a program load voltage generator for flash memories. It is based on an adaptive feedback loop which senses the current delivered to the memory cells during programming and adjusts the output voltage accordingly to compensate for the voltage drop caused by the programming current across the bit-line select transistors. The proposed circuit (silicon area=0.065 mm²) was integrated in a 0.8-μm CMOS 4 Mb flash memory device (0.6 μm in the matrix). Experimental evaluations showed that very effective compensation is achieved, with bit-line voltage kept at the desired value during the whole programming operation. A spread as small as 70 mV was measured between the single-bit and 16-b programming cases     

Overerase phenomena: an insight into flash memory reliability

The most important reliability issues related to the erasing operation in flash memories are, still today, caused by single bit failures. In particular, the overerase of tail and fast bits affects the threshold voltage distribution width, causing bit-line leakage that produces read/verify circuitry malfunctions, affects the programming efficiency due to voltage drop, and causes charge-pump circuitry failure. This brief overview explores the most important characteristics of these anomalous bits, their relation with the erratic erase phenomena and their impact on flash memory reliability. Identification techniques, experimental results, and physical models are also discussed.     

A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories

A new MLC NAND page architecture is presented as a breakthrough solution for sub-40-nm MLC NAND flash memories and beyond. To reduce cell-to-cell interference which is well known as the most critical scaling barrier for NAND flash memories, a novel page architecture including temporary LSB storing program and parallel MSB program schemes is proposed. A BL voltage modulated ISPP scheme was used as parallel MSB programming in order to reduce cell-to-cell interference caused by the order in which the cells are programmed. By adopting the proposed page architecture, the number of neighbor cells that are programmed after programming a selected cell in BL direction as well as their amount of T/th shift during programming can be suppressed largely without increasing memory array size. Compared to conventional architecture it leads to a reduction of BL-BL cell-to-cell interference by almost 100%, and of WL-WL and diagonal cell-to-cell interferences by 50% at the 60 nm technology node. The proposed architecture enables also to improve average MLC program speed performance by 11% compared with conventional architecture, thanks to its fast LSB program performance.     

Flash memory complexity

Driven by the demand for more versatile personal electronic devices such as cellular phones and handheld computers, flash memory has advanced rapidly to higher volume density and performance levels. Today, semiconductor manufacturers find a growing opportunity for more advanced flash memories delivered either as standalone flash devices; embedded as cores with logic in single-chip devices; or packaged as stacked dice with microcontrollers, logic, or static RAM. For flash manufacturers, however, success in these highly competitive markets requires tight control over the cost of test, despite rising device complexity. As flash memory grows in size, speed, and complexity, manufacturers are seeking more cost-effective, single-insertion test solutions capable of addressing resulting test challenges. With the development of new test architectures, manufacturers can more efficiently address emerging flash complexity using cost-effective, next-generation test platforms.