Vertically self-aligned buried junction formation for ultrahigh-density DRAM applications

In this letter, we present a novel junction integration scheme that enables vertical transistors to have high performance, low leakage, and easy scalability. Controlled solid-phase diffusion is used to form the vertically self-aligned buried strap junction of the vertical transistor. The electric field at the capacitor node junction is carefully optimized by creating a graded junction profile, resulted from a combination of out-diffusion from Arsenic-doped poly-silicon and Phosphorus-doped oxide. The Phosphorus-doped oxide serves as the dopant source for the vertical lightly doped drain, as well as the spacer for the high dose junctions. Integration of the self-aligned junctions into a vertical transistor dynamic random access memory (DRAM) process flow is presented. Significant improvement in the retention characteristics of a 256-Mb DRAM product confirms the applicability of this newly developed junction integration scheme for future DRAM generations.     

An evaluation of FUROX isolation technology for VLSI/nMOSFETfabrication

A defect-free near-zero bird's beak, fully recessed oxide (FUROX) field-isolation technology has been evaluated through the fabrication of VLSI/nMOSFETs. The FUROX process mainly consists of: (1) a thin nitrided oxide as the stress buffer layer and the interface sealing layer for local oxidation enhancement; and (2) a novel more-reliable nitride masking structure for a two-step field oxidation and a self-aligned field implantation. The elimination of the necking effect on positive photoresist and the improvement of critical dimension control for polysilicon gates using the planarized isolation have been demonstrated. Through electrical characterization of n⁺-p diodes and field and active transistors, the FUROX devices have been shown to provide low leakage-current level, good isolation property, and large recovery of the effective channel width (1.4 μm). Therefore, the serious narrow-width effects that exist in conventional LOCOS (local oxidation of silicon) isolated have been effectively reduced. Using histogram analysis, the reliability of the masking structure had hence good uniformity of device properties for FUROX isolation have been exhibited. The successful fabrication of FUROX devices with W_eff=0.6 μm clearly demonstrates that FUROX isolation technology is greatly superior to conventional LOCOS     

Planarization of amorphous silicon thin film transistors by liquidphase deposition of silicon dioxide

A planarized device structure was developed for amorphous silicon thin film transistors to overcome the gate leakage problem. Utilizing the liquid phase deposition technique, a silicon oxide film with thickness exactly equal to the gate height was grown around the gate to planarize the surface for the fabrication of inverted staggered thin film transistors. The planarized thin film transistor has smaller leakage current and better performance, i.e., field effect mobility, subthreshold swing, etc. This novel process has a potential to improve the yield of large area liquid crystal display     

一种基于刻蚀的SOI深槽介质隔离工艺

介绍了一种基于刻蚀的SOI深槽介质隔离(DTI)工艺。该工艺采用BOSCH刻蚀、兆声清洗、多晶硅回填、刻蚀平坦化等技术,制作流程简单。其介质隔离击穿电压可以根据电路的需要进行调整,并可根据氧化层厚度进行预测。其介质隔离漏电流极低。     

用深反应离子刻蚀和介质填充技术制造具有高深宽比的超深电隔离槽

提出了一种利用深反应离子刻蚀(DRIE)和电介质填充方法来制造具有高深宽比的深电学隔离槽的新型技术.还详细讨论了DRIE刻蚀参数与深槽侧壁形状之间的关系,并作了理论上的阐述.采用经过参数优化的DRIE刻蚀深硅槽,并用反应离子刻蚀(RIE)对深槽开口形状进行修正,制造了具有理想侧壁形状的深槽,利于介质的完全填充,避免产生空洞.电隔离槽宽5μm,深92μm,侧壁上有0.5μm厚的氧化层作为电隔离材料.I-V测试结果表明该隔离结构具有很好的电绝缘特性:0～100V偏压范围内,电阻大于1011Ω,击穿电压大于100V.电隔离深槽被首次应用于体硅集成微机械陀螺仪上的微机械结构与电路之间的电气隔离与机械连接,该陀螺的性能得到了显著提高.     

100V高压CMOS工艺关键技术的研究

提出了一种新的双栅氧(dual gate oxide,DGO)工艺,有效提高了薄栅氧器件与厚栅氧器件的工艺兼容性,同时提高了高低压器件性能的稳定性.在中国科学院微电子研究所0.8μm n阱标准CMOS工艺基础上设计出高低压兼容的100V高压工艺流程,并流片成功.实验结果表明,高压n管和高压p管的关态击穿电压分别为168和-158V,可以在100V高压下安全工作.     

Investigations of Key Technologies for 100V HVCMOS Process

提出了一种新的双栅氧(dual gate oxide,DGO)工艺,有效提高了薄栅氧器件与厚栅氧器件的工艺兼容性,同时提高了高低压器件性能的稳定性.在中国科学院微电子研究所0.8μm n阱标准CMOS工艺基础上设计出高低压兼容的100V高压工艺流程,并流片成功.实验结果表明,高压n管和高压p管的关态击穿电压分别为168和-158V,可以在100V高压下安全工作.     

Advanced `contact engineering' for submicron VLSI multilevelmetallization

Two contact engineering methods developed for submicron contact openings are described. The two methods, SCOPE (simultaneous contact and planarization etch) and PACE (planarization after contact etch), interchange the process sequences of dielectric planarization and contact etch to achieve uniform contact etch. Both etching processes eliminate the need for oxide reflow thereby minimizing the thermal budget after source/drain formation. Since the dielectric is planarized either during the contact etch (e.g., with SCOPE) or after contact etch (e.g., with PACE), the need for extensive overetching of the oxide due to the dissimilar contact depths is also eliminated. As a result, contact resistance and leakage currents are significantly reduced in comparison to results obtained with dielectrics planarized before etching. In addition, etching of field oxide due to pattern misalignment is minimized since the contacts are of similar depth     

A new junction termination method employing shallow trenches filled with oxide

A new junction termination method employing shallow trenches filled with oxide, which successfully decreased the junction termination area, is proposed and fabricated without any complicated process such as Si-deep etching. Shallow trenches between the floating field limiting rings successfully redistributed the single electric field peak into two peaks so that the breakdown voltage could be increased with the same junction termination area. The experimental results show that the proposed method decreased the junction termination area by more than 25% compared to a conventional field limiting ring structure when breakdown voltages are equal.     

Hot-carrier degradation of LDD MOSFET's with gate oxynitride grownin N2O

Hot carrier immunity (HCI) of single drain (SD) and lightly doped drain (LDD) n-MOSFET's with gate oxide and N₂O gate oxynitride was compared. Gate oxynitride shows better HCI than gate oxide in SD devices but comparable in LDD devices. We show that oxide grown during the poly-silicon oxidation process after gate poly-silicon definition plays an important role in determining the hot carrier resistance of LDD n-MOSFET's with N₂O gate oxynitride     

A 0.8-μm CMOS technology for high-performance ASIC memory andchannelless gate array

A 0.8-μm polycide-gate, double-layer-metal CMOS technology is described. Nominal device gate lengths down to 0.8 (±0.2) μm are used for both n- and p-channel transistors. Compact isolation, 175-A gate oxide grown in dry/wet/dry ambient, shallow-junction halo-implanted lightly doped drain n and p devices, TiN contact barrier, and a planarized double-layer-metal process are all integrated and demonstrated with a 0.8-μm full-CMOS 16K SRAM (static random-access memory) circuit. The device process integrity, design margins, performance, reliability, product yield and speed enhancement are all discussed in detail     

A low-capacitance bipolar/BiCMOS isolation technology. II. Circuitperformance and device self-heating

For pt. 1 see ibid., vol. 41, no. 8, p. 1379-87 (1994). Device and circuit results from transistors fabricated with a novel bipolar isolation technology are presented and discussed. The isolation structure, called sequentially planarized interlevel isolation technology (SPIRIT), is fabricated by using a combination of selective epitaxial growth of silicon and a preferential polishing technique as the key process elements. This structural concept aims for reduced collector-substrate and collector-base capacitances, as well as a lower extrinsic base contact resistance, in a partial-SOI structure without significantly increasing the device temperature during operation. The feasibility of the isolation structure is demonstrated through ECL ring oscillators with gate delays of 23.6 ps at 0.72 mA and 47 ps at 0.23 mA. The temperature contours for SPIRIT and other bipolar isolation structures are simulated by using a finite-element method. It is shown that the capacitance versus self-heating tradeoff of SPIRIT is significantly improved over that of conventional trench or SOI isolation structures     

Oxidation-induced defect generation in advanced DRAM structures

Structures containing deep-trenched storage capacitors and shallow-trench isolation were examined in patterns suitable for future generation dynamic RAMs (DRAMs). These same effects were also examined in similar structures which included only the shallow isolation trenches. Observed was a strong interaction between the deep and shallow trenches, which makes structures which incorporate both types much more susceptible to oxidation-induced defect generation than those without deep trenches. It was observed that at higher oxidation temperatures, more oxide can be grown before defects are generated. This is interpreted as a combination of more-efficient visco-elastic relaxation in the oxide and a lower differential oxidation rate between the {110} trench sidewalls and the {100} planar surface at higher temperatures. It was also observed that substantial defect immunity can be obtained by incorporating an oxidation barrier in the trench structures. An overall processing strategy to eliminate defect generation in these advanced structures is suggested     

The formation of Ti-polycide gate structure with high thermalstability using chemical-mechanical polishing (CMP) planarizationtechnology

A planarized Ti-polycide gate structure with high thermal stability has been developed using a chemical-mechanical polishing (CMP) process for the application of high-speed DRAM devices. For a given gate length and without any thermal annealing, the planarized Ti-polycide structure developed via a novel gate line formation technology manifested a substantially lower gate line resistance than that produced by a conventional processing method. In addition, the agglomeration of the TiSi₂ gate in a deep submicron regime was suppressed even after high-temperature cycling at 850°C for 300 min, owing to a negligible local stress at the corner of the active and field region     

New High-Voltage ( $>$ 1200 V) MOSFET With the Charge Trenches on Partial SOI

A novel silicon-on-insulator (SOI) high-voltage MOSFET structure and its breakdown mechanism are presented in this paper. The structure is characterized by oxide trenches on the top interface of the buried oxide layer on partial SOI (TPSOI). Inversion charges located in the trenches enhance the electric field of the buried layer in the high-voltage blocking state, and a silicon window makes the depletion region spread into the substrate. Both of them modulate the electric field in the drift region; therefore, the breakdown voltage (BV) for a TPSOI LDMOS is greatly enhanced. Moreover, the Si window alleviates the self-heating effect. The influences of the structure parameters on device characteristics are analyzed for the proposed device structure. The TPSOI LDMOS with BV > 1200 V and the buried-layer electric field of E_I > 700 V/ mum is obtained by the simulation on a 2-mum-thick SOI layer over 2-mum-thick buried oxide layer, and its maximal temperature reduces by 19 and 8.7 K in comparison with the conventional SOI and partial SOI devices.     

Nitrogen-doped poly spacer local oxidation

A novel isolation technique which consists of a modified local oxidation of silicon (LOCOS) process with a nitrogen-doped amorphous-Si spacer has been developed. Nitrogen doping of amorphous-Si reduces its oxide growth rate. This isolation process shows the least encroachment, smallest maximum stress, and a deeper field oxide recess as compared to standard LOCOS or poly spacer LOCOS. The oxidation of nitrogen-doped amorphous-Si also has been simulated by an equivalent stacked layer     

A novel self-aligned isolation process for VLSI

We have developed a novel NMOS process for VLSI isolation. The process employs an RIE of the field oxide followed by a metal liftoff and a high-energy boron sheet implant. The energy of the implant and the metal thickness are selected such that the boron penetrates the field oxide, but not the metal. Performing the isolation doping after growing the field oxide eliminates encroachment of the isolation doping into the channel end while simultaneously providing a self-aligned channel stop. The doping concentration in the channel region is determined by implants that are independent of the doping concentration in the channel stop area. With this technique, we have obtained excellent device performance as well as rigorous device isolation. Even at the isolation spacing of 0.7 µm, there was <1-pA leakage at 5 V. The active devices exhibit minimal body effect coefficients (0.1-0.2), good subthreshold behavior (80 mV/DEC), and low junction capacitance. The experimental data is confirmed by two-dimensional analysis.     

Direct Moat Isolation for VLSI

Device isolation is a major factor in determining the circuit packing density in VLSI. The scalability of device isolation by local oxidation of silicon (LOCOS) is limited by the large encroachment, including both physical and electrical, into the active device area resulting from lateral oxidation (bird's beaking) at the edge of isolation oxide and channel stop diffusion into the active device region. An alternative isolation technique is to form the active device area by patterning a thick field oxide uniformly grown or deposited on the silicon substrate. Such a direct moat isolation scheme makes more efficient use of the silicon area by reducing encroachment considerably and thus allowing closer packing of active devices than the LOCOS approach. Direct moat isolation process approaches for VLSI design rules are discussed. Short-channel effects on the subthreshold characteristics of the parasitic devices are studied using a two-dimensional model and compared with experimental measurements. Good device isolation is demonstrated in a parasitic device with a field oxide thickness of 550 nm and a minimum moat-to-moat spacing of 2 /spl mu/m.     

Embedded benzocyclobutene in silicon: An integrated fabrication process for electrical and thermal isolation in MEMS

This paper reports a novel fabrication process to develop planarized isolated islands of benzocyclobutene (BCB) polymer embedded in a silicon substrate. Embedded BCB in silicon (EBiS) can be used as an alternative to silicon dioxide in fabrication of electrostatic micromotors, microgenerators, and other microelectromechanical devices. EBiS takes advantage of the low dielectric constant and thermal conductivity of BCB polymers to develop electrical and thermal isolation integrated in silicon. The process involves conventional microfabrication techniques such as photolithography, deep reactive ion etching, and chemical mechanical planarization (CMP). We have characterized CMP of BCB polymers in detail since CMP is a key step in EBiS process. Atomic force microscopy (AFM) and elipsometry of blanket BCB films before and after CMP show that higher polishing down force pressure and speed lead to higher removal rate at the expense of higher surface roughness, non-uniformity, and scratch density. This is expected since BCB is a softer material compared to inorganic films such as silicon dioxide. We have observed that as the cure temperature of BCB increases beyond 200 °C, the CMP removal rate decreases drastically. The results from optical microscopy, scanning electron microscopy, and optical profilometry show excellent planarized surfaces on the EBiS islands. An average step height reduction of more than 95% was achieved after two BCB deposition and three CMP steps.     

多晶硅微机械开关

利用LPCVD SiO2和多晶硅作牺牲层和悬臂梁技术,解决了多晶硅应力释放问题以及微机械开关工艺与IC工艺兼容技术问题,获得了淀积弱张应力的多晶硅膜的最佳工艺条件,研制出多晶硅微机械开关.初步测试出其开关的开启电压为89V,开关速度为5μs,这为研制用于雷达和通讯的全单片集成的RF MEMS开关系统打下了基础.