一种基于BSIM-CMG的FinFET变容管模型

提出了一种适用于FinFET变容管的建模方法.在BSIM-CMG的基础上,模型采用衬底模型和外围寄生模型来表征变容管的射频寄生效应.提出了具体的参数提取方法,将测试的S参数导入到安捷伦IC-CAP建模软件提取参数,测试结构引入高频寄生采用(open+ short)去嵌方法进行去嵌.通过调节模型参数拟合测试曲线得到FinFET变容管模型.该模型可精确表述FinFET变容管全工作区域特性,解决传统MOS变容管模型无法准确描述三维FinFET器件变容特性的问题.模型和模型参数提取方法采用20个硅鳍、16个栅指、158 nm栅长、578 nm栅宽的FinFET变容管进行建模验证,模型仿真和测试所得C-V,R-V和S参数特性吻合良好.     

集成PMOS管变容特性分析与仿真建模

为适应PMOS变容管在集成电路设计中的晶体管级仿真,在分析MOS变容管特性的基础上,通过确定关键点、以曲线拟合的方法建立与工艺参数相关的PMOS集成变容管高频特性模型。选用Charted 0.35μm这个特定的工艺库,并离散地改变电容连接的PMOS静态偏压、用HSpice仿真并对寄生电容提取后描绘出变容特性的准静态曲线;用Matlab对所建的简化高频变容模型进行仿真、得出高频变容曲线。仿真与理论结果相比较表明：PMOS管变容特性曲线与理论曲线的变化趋势吻合;2种仿真对变容显著区吻合较好。从而证明了PMOS集成变容管高频简化模型的正确性。     

MOS管变容特性研究及振荡频率估计

采用软件模拟及仿真的方法,对MOS管变容的特性进行了分析,根据MOS管的变容特性得出一种VCO的频率精确估计方法。仿真实验表明,该方法具有较高的精确度。在电路的设计中可用该方法预测频率,或者提供元件的参考参数从而提高设计效率,降低设计成本。     

RF-CMOS建模:一种改进的累积型MOS变容管模型

提出一种改进的累积型MOS变容管射频模型,改进后模型方程可精确描述累积型MOS变容管全工作区域特性;模型方程连续,且任意阶次可导,至少三阶导数求解结果可实现与测试结果的精确拟合,解决了原模型可导但导数错误、变阻方程不连续等问题.模型最终应用到采用CSM(Chartered Semiconductor Manufacture Ltd)0.25μm RF-CMOS工艺制造的一30栅指(每指尺寸为长L=1μm,宽W=4.76μm)累积型MOS变容管建模中,测量和仿真所得C-V,R-V特性,品质因素以及高达39GHz S参数对比结果验证了模型的良好精度.     

RF-CMOS建模:一种改进的累积型MOS变容管模型

提出一种改进的累积型MOS变容管射频模型,改进后模型方程可精确描述累积型MOS变容管全工作区域特性;模型方程连续,且任意阶次可导,至少三阶导数求解结果可实现与测试结果的精确拟合,解决了原模型可导但导数错误、变阻方程不连续等问题.模型最终应用到采用CSM(Chartered Semiconductor Manufacture Ltd)0.25μm RF-CMOS工艺制造的一30栅指(每指尺寸为长L=1μm,宽W=4.76μm)累积型MOS变容管建模中,测量和仿真所得C-V,R-V特性,品质因素以及高达39GHz S参数对比结果验证了模型的良好精度.     

一种简化衬底模型的SOI MOS变容管模型

提出一种适用于反型层RF SOI MOS 变容管行为表征模型。在BSIMSOI的基础上,模型采用简化的衬底模型和外围射频寄生模型来表征变容管的射频寄生效应,同时采用T、π互转的方式提出参数提取算法。模型最终应用到华虹宏力SOI工艺提供的不同栅指,每栅指长度为1.6um、宽度为5 um的MOS变容管器件,并且在15GHz以下,模型与测量数据的CV、QV以及S参数有较好的拟合。在高频情况下,模型既保证了精度又解决了参数提取困难等问题。     

基于积累型MOS变容管的射频压控振荡器设计

随着移动通信技术的发展,射频（RF）电路的研究引起了广泛的重视。采用标准CMOS工艺实现压控振荡器（VCO）,是实现RF CMOS集成收发机的关键。过去的VCO电路大多采用反向偏压的变容二极管作为压控器件,然而在用实际工艺实现电路时,会发现变容二极管的品质因数通常都很小,这将影响到电路的性能。于是,人们便尝试采用其它可以用CMOST艺实现的器件来代替一般的变客二极管,MOS变容管便应运而生了。     

一种新型MOS变容管在射频压控振荡器中的应用

基于0.5μm工艺，设计了一个工作频率在1.8GHz，相位噪声在偏移量为500kHz时小于-100dBc/Hz的压控振荡器（VCO）。并将一个普通的压控MOS变容管改进为只工作在反型区的压控MOS变容管。将这两种MOS电容分别应用到该VCO电路中。结果表明，采用反型模式压控MOS变容管的VCO电路具有更大的调谐范围，调谐曲线由之前的反复变化变为单调变化，并且对电路的相位噪声也起到了抑制作用。     

用积累型MOS变容管实现的2.4GHz 0.25μm CMOS全集成压控振荡器

基于TSMC 0.25μm CMOS工艺,将一个普通MOS管改进为工作在积累区的MOS变容管,实现了一工作于2.4GHz的全集成压控振荡器(VCO).测试结果表明,采用积累型MOS变容管的VCO具有较大的调谐范围.在2.5V工作电压下,控制电压从0～2.2V,VCO的频率调节范围为2.210～2.484GHz,在2.4GHz时相位噪声为-105dBc/Hz@600kHz,输出功率为-7.55dBm,电流损耗为7mA.芯片面积约为0.35mm2.     

短沟道MOS阈值电压物理模型

通过求解二维泊松方程推导了一个简洁的短沟道 MOS的阈值电压模型 ,得到的 DIBL因子可用于分析参数对短沟道效应的影响。模拟的结果能很好地与数值模拟器 MINIMOS的结果符合     

On the use of MOS varactors in RF VCOs

This paper presents two 1.8 GHz CMOS voltage-controlled oscillators (VCOs), tuned by an inversion-mode MOS varactor and an accumulation-mode MOS varactor, respectively. Both VCOs show a lower power consumption and a lower phase noise than a reference VCO tuned by a more commonly used diode varactor. The best overall performance is displayed by the accumulation-mode MOS varactor VCO. The VCOs were implemented in a standard 0.6 μm CMOS process     

High performance MOS varactor SPICE model

A model is for presented a three-terminal MOS varactor for RF applications. The accuracy of the MOS varactor model is demonstrated by comparing simulation and measured device data at room and high temperatures. The relative mean error of the S-parameters between the measured and simulated data are less than 4%.     

A 110–140 GHz Millimeter-Wave VCO Using Varactor and Bulk Effective Technique in 65 nm CMOS Process

In this paper, an enhanced voltage controlled oscillator (VCO) at center frequency 125 GHz with tuning rang of 24% is presented. The proposed idea is based on the tuning capacitance using MOS varactor. The structure is consisted of applying an MOS varactor capacitor to the drain and bulk (in parallel) of NMOS transistor in 65 nm CMOS standard technology. The obtained output of the proposed VCO at 2nd harmonic is tunable at 110–140 GHz frequency with applying?±?1.2 input tuning voltage. Simulation results of the proposed circuit are obtained after extracting post layout (with total chip size of 0.07 mm²) and confirm theoretical results. Compared to the resent designs, the obtained results indicate that the proposed circuit has high tuning range, low die area and a good figure of merit @ 1.2 power supply voltage.

     

Large-signal analysis of MOS varactors in CMOS -G/sub m/ LC VCOs

MOS varactors are used extensively as tunable elements in the tank circuits of RF voltage-controlled oscillators (VCOs) based on submicrometer CMOS technologies. MOS varactor topologies include conventional D = S = B connected, inversion-mode (I-MOS), and accumulation-mode (A-MOS) structures. When incorporated into the VCO tank circuit, the large-signal swing of the VCO output oscillation modulates the varactor capacitance in time, resulting in a VCO tuning curve that deviates from the dc tuning curve of the particular varactor structure. This paper presents a detailed analysis of this large-signal effect. Simulated results are compared to measurements for an example 2.5-GHz complementary -G/sub m/ LC VCO using I-MOS varactors implemented in 0.35-/spl mu/m CMOS technology.     

IOGHz 0.25μm CMOS LC压控振荡器

采用标准0.25μm CMOS工艺实现了10GHz LC压控振荡器.为了适应高频工作,并实现低相位噪声,该压控振荡器采用了手动优化的带中心抽头的对称电感,将A-MOS变容二极管与无源金属-绝缘层-金属电容串联,并采用了带LC滤波器的尾电流源.测试结果显示,当振荡频率为10.2GHz时,在1MHz频偏处相位噪声为-103.2dBc/Hz,调谐范围为11.5%.供电电压为3.3V时,核心电路功耗为9.0mW.芯片面积为0.67mm×0.58mm.     

1.9 GHz low loss varactor diode pre-distorter

Pre-distorters implemented at circuit level using series diodes have a high loss. The method presented here combines source/load second harmonic control with a parallel connected varactor diode. A reduction of 15 dB in the spectral regrowth at 1.9 GHz is achieved with a low loss of 2 dB due to the varactor diode     

Discrete-time parametric amplification based on a three-terminal MOS varactor: analysis and experimental results

This paper discusses discrete-time parametric amplification based on large-signal operation of a three-terminal MOS varactor. The principle of operation is described in detail and analytical estimates of performance are derived. Detailed measurements are reported for a prototype implemented in standard digital CMOS technology. It is demonstrated that the technique can be used to provide micropower, low-gain, low-noise, large-signal amplification.     

Modeling and characterization of a 5.2 GHz VCO for UWB applications in 0.13 μm CMOS process

This paper describes a 5.2 GHz voltage-controlled oscillator (VCO) as a key component in RF transceivers. The circuit includes a complementary cross-coupled MOSFET as a negative conductance, beside a tank circuit which consists of an optimal on-chip spiral inductor (L), and an accumulation mode MOS varactor (C(V)). A model for phase noise and figure merit is introduced and verified through simulation in a standard 0.13 μm CMOS process. The VCO core drew a 4.2 mA of current from a 1.2 V power supply and a phase noise of −98.5 dBc/Hz at 1 MHz offset from the 5.2 GHz carrier was calculated. The whole performance of the circuit specifically the tuning range was found to be 26%.     

MOS varactor modeling with a subcircuit utilizing the BSIM3v3 model

This paper presents a subcircuit model for an MOS varactor based on the BSIM3v3 model suitable for simulator implementation within circuit-design environments. The development of the model and BSIM3v3 model parameter settings are discussed in detail. By varying the length (L) of the device, C_MAX/C_MIN ratios as high as five or minimum quality factors of 21.5 at 2.4 GHz can be achieved using a standard 0.35 μm CMOS process. The investigation of different geometries resulted in a tradeoff between capacitance tuning and quality factor. A medium length varactor has been characterized