A 2.4-GHz sub-mW CMOS receiver front-end for wireless sensors network

A 2.4-GHz fully integrated CMOS receiver front-end using current-reused folded-cascode circuit scheme is presented. A configuration utilizing vertically stacked low-noise amplifier (LNA) and a folded-cascode mixer is proposed to improve both conversion gain and noise figure suitable for sub-mW receiver circuits. The proposed front-end achieves a conversion gain of 31.5dB and a noise figure of 11.8dB at 10MHz with 500-/spl mu/A bias current from a 1.0-V power supply. The conversion gain and noise figure improvements of the proposed front-end over a conventional merged LNA and single-balanced mixer are 11dB and 7.2dB at 10MHz, respectively, with the same power consumption of 500/spl mu/W.     

2.4 GHz ISM-Band Receiver Design in a 0.18 μm Mixed Signal CMOS Process

This letter presents the design and measurement results of a fully integrated CMOS receiver front-end and voltage controlled oscillator (VCO) for 2.4 GHz industrial, scientific and medical (ISM)-band application. For low cost design, this receiver has been fabricated with a 0.18 mum thin metal CMOS process with a top metal thickness of only 0.84 mum. The receiver integrates radio frequency (RF) front-end (a single-ended low-noise amplifier (LNA) with on-chip spiral inductors and a double balanced down conversion mixer), VCO and local oscillation buffers on a single chip together with an internal output buffer. To obtain the high-quality factor inductor in LNA, VCO and down conversion mixer design, patterned-ground shields (PGS) are placed under the inductor to reduce the effect from image current of resistive Si substrate. Moreover, in VCO and mixer design, due to the incapability of using thick top metal layer of which the thickness is over 2 mum, as used in many RF CMOS process, the structure of dual-metal layer in which we make electrically short circuit between the top metal and the next metal below it by a great number of via arrays along the metal traces is adopted to compensate the Q -factor degradation. In this letter, the receiver achieves a conversion gain of 23 dB, noise figure of 8.1 dB and P1 dB of -20 dBm at 39 MHz with 21 mW power dissipation from a 1.8 V power supply. It occupies a whole circuit area of 2 mm².     

A CMOS passive mixer with low flicker noise for low-power direct-conversion receiver

A CMOS passive mixer is designed to mitigate the critical flicker noise problem that is frequently encountered in constituting direct-conversion receivers. With a unique single-balanced passive mixer design, the resulted direct-conversion receiver achieves an ultralow flicker-noise corner of 45 kHz, with 6 dB more gain and much lower power and area consumption than the double-balanced counterpart. CMOS switches with a unique bias-shifting network to track the LO DC offset are devised to reduce the second-order intermodulation. Consequently, the mixer's IIP2 has been greatly enhanced by almost 21 dB from a traditional single-balanced passive mixer. An insertion compensation method is also implemented for effective dc offset cancellation. Fabricated in 0.18 /spl mu/m CMOS and measured at 5 GHz, this passive mixer obtains 3 dB conversion gain, 39 dBm IIP2, and 5 dBm IIP3 with LO driving at 0 dBm. When the proposed mixer is integrated in a direct-conversion receiver, the receiver achieves 29 dB overall gain and 5.3 dB noise figure.     

3.6 mw low power wireless RF receiver front end using creative current recycle technique

This paper presents the design of low noise amplifier and mixer (LIXER) circuit for wireless receiver front ends using 65 nm CMOS technology. The circuit is implemented with CMOS transistors and uses 65 nm CMOS process. Proposed LIXER circuit achieves a maximum gain of 25 dB and DSB noise figure of 3.5 dB. In the given circuit, current shunt paths had created by using LC tank circuit with transistors Q5 and Q6. By using the creative current recycle technique circuit consumes 3.6 mW power with 1.2 V power supply. The operating frequency of the proposed structure is 2.4 GHz with 25 dB conversion gain and ?13 dBm IIP3. The operating of the receiver front end is 2.4 GHz is used for IEEE 802.11a WLAN, Bluetooth, and ZigBee applications.     

用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

A low power direct conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise

A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 μm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and −2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.     

An I/Q mixer with an integrated differential quadrature all-pass filter for on-chip quadrature LO signal generation

A down-conversion in-phase/quadrature (I/Q) mixer employing a folded-type topology, integrated with a passive differential quadrature all-pass filter (D-QAF), in order to realize the final down-conversion stage of a 60 GHz receiver architecture is presented in this work. Instead of employing conventional quadrature generation techniques such as a polyphase filter or a frequency divider for the local oscillator (LO) of the mixer, a passive D-QAF structure is employed. Fabricated in a 65 nm CMOS process, the mixer exhibits a voltage gain of 7-8 dB in an intermediate frequency (IF) band ranging from 10 MHz-1.75 GHz. A fixed LO frequency of 12 GHz is used to down-convert a radio frequency (RF) band of 10.25-13.75 GHz. The mixer displays a third order input referred intercept point (IIP₃) ranging from -8.75 to -7.37 dBm for a fixed IF frequency of 10 MHz and a minimum single-sideband noise figure (SSB-NF) of 11.3 dB. The mixer draws a current of 6 mA from a 1.2 V supply voltage dissipating a power of 7.2 mW.     

A merged CMOS LNA and mixer for a WCDMA receiver

A low-noise amplifier (LNA) and mixer circuit in 0.35-/spl mu/m CMOS operates at 2.1 GHz. Merging the LNA and mixer lowers the number of transistors in the signal path and thereby also the nonlinearity and power consumption. The circuit meets the specifications for a direct conversion wide-band code-division multiple access (WCDMA) receiver. Its noise figure is 3.4 dB (5kHz to 5MHz), the total conversion gain is 23 dB, the third-order input-referred intercept point is -1.5 dBm, and the local oscillator leakage to the antenna is less than -71 dBm. The fully differential circuit takes 8 mA from a 2.7-V supply.     

A 5.25-GHz low-power down-conversion mixer in 0.18-μm CMOS technology

A 5.25 GHz low voltage, high linear and isolated mixer using TSMC 0.18 μm CMOS process for WLAN receiver was investigated. The paper presents a novel topology mixer that leads to better performance in terms of linearity, isolation and power consumption for low supply voltage. The measuring results of the proposed mixer achieve: 7.6 dB power conversion gain, 11.4 dB double side band noise figure, 3 dBm input third-order intercept point, and the total dc power consumption of this mixer including output buffers is 2.45 mW from a 1 V supply voltage. The current output buffer is about 2 mW, the excellent LO-RF, LO-IF and RF-IF isolation achieved up to 37.8, 54.8 and 38.2 dB, respectively.     

A 2.7-V 900-MHz CMOS LNA and mixer

A CMOS low-noise amplifier (LNA) and a mixer for RF front-end applications are described. A current reuse technique is described that increases amplifier transconductance for the LNA and mixer without increasing power dissipation, compared to standard topologies. At 900 MHz, the LNA minimum noise figure (NF) is 1.9 dB, input third-order intercept point (IIP3) is -3.2 dBm and forward gain is 15.6 dB. With a 1-GHz local oscillator (LO) and a 900-MHz RF input, the mixer minimum double sideband noise figure (DSB NF) is 5.8 dB, IIP3 is -4.1 dBm, and power conversion gain is 8.8 dB. The LNA and mixer, respectively, consume 20 mW and 7 mW from a 2.7 V power supply. The active areas of the LNA and mixer are 0.7 mm×0.4 mm and 0.7 mm×0.2 mm, respectively. The prototypes were fabricated in a 0.5-μm CMOS process     

A low-power oscillator mixer in 0.18-/spl mu/m CMOS technology

A downconversion double-balanced oscillator mixer using 0.18-/spl mu/m CMOS technology is proposed in this paper. This oscillator mixer consists of an individual mixer stacked on a voltage-controlled oscillator (VCO). The stacked structure allows entire mixer current to be reused by the VCO cross-coupled pair to reduce the total current consumption of the individual VCO and mixer. Using individual supply voltages and eliminating the tail current source, the stacked topology requires 1.0-V low supply voltage. The oscillator mixer achieves a voltage conversion gain of 10.9 dB at 4.2-GHz RF frequency. The oscillator mixer exhibits a tuning range of 11.5% and a single-sideband noise figure of 14.5 dB. The dc power consumption is 0.2 mW for the mixer and 2.94 mW for the VCO. This oscillator mixer requires a lower supply voltage and achieves a higher operating frequency among recently reported Si-based self-oscillating mixers and mixer oscillators. The mixer in this oscillator mixer also achieves a low power consumption compared with recently reported low-power mixers.     

A Highly Linear SAW-Less CMOS Receiver Using a Mixer With Embedded Tx Filtering for CDMA

An embedded filtering passive (EFP) mixer is used to overcome transmitter power leakage in a receiver without the use of a SAW filter. The receiver IC exhibits more than ${+}$ 60 dBm of Rx IIP$_{2}$ , 2.4 dB Rx noise figure, and ${+}$77 dB of Triple Beat (TB) with 45 MHz offset transmit leakage at 900 MHz Rx frequency while consuming only 18 mA from a 2.1 V supply. Thanks to the embedded filtering passive mixer, the proposed receiver IC shows an additional 15 dB Tx rejection compared to a conventional receiver. The additional Tx rejection improved the IIP $_{2}$ by 10 dB and TB by 30 dB. The complete receiver consists of a differential LNA employing an active post-distortion (APD), I/Q embedded filtering passive mixer, two TIAs for I/Q outputs. The fabricated receiver IC occupies 2.25 mm$^{2}$ including bonding pads, ESD devices, local oscillator (LO) input buffer, frequency divider, and mixer drivers. The receiver is fabricated using a 0.18 $mu$m CMOS process with 5 metal and 1 poly (5M1P) layer.      

A 1.83 GHz 28.5 dBm CMOS Power Up-Mixer

A power up-mixer is proposed in this letter. A merged CMOS linear power amplifier (PA) and mixer allows low current consumption and smaller chip size than a conventional integrated transmitter including a mixer and a CMOS linear PA. The chip is fabricated in a 0.18 $mu{rm m}$ CMOS process and in an integrated-passive-device. Measurements show a drain efficiency of 27% at 27.2 dBm of 1 dB compression point (P1dB) output power from 1.75 to 1.95 GHz. Power conversion gain is 26.4 dB and LO leakage is $-$43 dBc.      

The Design of Low LO-Power 60-GHz CMOS Quadrature-Balanced Self-Switching Current-Mode Mixer

This letter describes the analysis and measurement of a complementary metal-oxide semiconductor (CMOS) quadrature-balanced current-mode mixer with a 90^deg branch-line hybrid coupler and self-switching current-mode devices. The proposed mixer, using 0.13 mum 1P8M CMOS technology, can downconvert a 60 GHz RF signal to a 2 GHz intermediate frequency (IF) signal, with a local-oscillator power of 0 dBm at 58 GHz. In the design, the mixer had a single-end conversion gain of 1 dB and an input-referred 1 dB compression point of 2 dBm. The LO-RF isolation of the mixer can achieve -37 dB while using 3 mA from a supply voltage of 1.2 V.     

60 GHz double-balanced up-conversion mixer on 130 nm CMOS technology

A millimetre-wave Gilbert-cell up-conversion mixer using standard 130 nm CMOS technology is presented. This mixer has a power conversion gain of better than 2 dB and has the highest reported OP 1 dB of -5.6 dBm when driven with a LO power of 0 dBm. The LO to RF isolation are better than 37 dB for LO from 57 to 65 GHz. Microstrip lines were employed for the matching network design at the mixer output. This is believed to be the first CMOS Gilbert-cell up-conversion mixer operating in the 60 GHz frequency band using fundamental LO.     

一种高性能CMOS单片中频接收机

研制了一种CM O S低压低功耗中频接收机芯片,它包含混频器、限幅放大器、解调器以及场强指示、消音控制等模块,可用于短距离的FM/FSK信号的接收和解调。该接收机采用1st s ilicon 0.25μm CM O S工艺,芯片的测试结果表明整机接收灵敏度为-103 dBm,最高输入射频频率可以达到100 MH z,解调器的线性解调范围为±10 kH z,典型鉴频灵敏度为40 mV/kH z,输入FM信号(调频指数3,信号频率1 kH z)时解调信号的SFDR为41.3 dB。芯片的工作电源电压范围为2~4 V,工作电流3 mA,有效面积0.25 mm2。     

A low voltage current mode CMOS integrated receiver front-end for GPS system

This paper presents a low voltage, 1.6 GHz integrated receiver front-end which is implemented by the standard 0.35 μm, 3M2P CMOS technology. The receiver consists of a transconductance low noise amplifier (G_m-LNA), a down conversion current mode mixer and a voltage-controlled oscillator using accumulation-mode MOS varactor (A-MOS VCO). A current mode mixer is used to reduce the supply voltage to 1 V. A specially designed G_m-LNA converts RF input voltage to RF input current for the current mode mixer. This could eliminate an unnecessary I–V, V–I conversion and reduce the non-linearity contribution. Moreover, a low voltage A-MOS VCO, with a good phase noise and wide tuning frequency range, is used to generate a required oscillating frequency for the receiver. The integrated receiver front-end has a measured power conversion gain of 11.4 dB, an input referred third-order intercept point (IIP₃) of 6.1 dBm, and a noise figure of 5.87 dB. The measured total power consumption is 40.9 mW with 1 V supply.     

A Fully Integrated 60GHz Four Channel CMOS Receiver with 7GHz Ultra-Wide Bandwidth for IEEE 802.11ad Standard

In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60GHz millimeter wave （mmW） band is designed and implemented in 90nm CMOS technology. The 60GHz receiver is designed based on the super-heterodyne architecture consisting of a low noise amplifier （LNA） with inter-stage peaking technique, a single- balanced RF mixer, an IF amplifier, and a double-balanced I/Q down-conversion IF mixer. The proposed 60GHz receiver frontend derives from the sliding-IF structure and is designed with 7GHz ultra-wide bandwidth around 60GHz, supporting four 2.16GHz receiving channels from IEEE 802.1lad standard for next generation high speed Wi- Fi applications. Measured results show that the entire receiver achieves a peak gain of 12dB and an input 1-dB compression point of -14.SdBm, with a noise figure of lower than 7dB, while consumes a total DC current of only 60mA from a 1.2V voltage supply.     

A 10–35 GHz Low Power Bulk-DrivenMixer Using 0.13 $mu$m CMOS Process

10-35 GHz doubly balanced mixer using a 0.13-mum CMOS foundry process is presented in this letter. Using the bulk-driven topology, the number of transistors of the doubly balanced mixer is reduced; thus the mixer can achieve a low supply voltage and low power consumption. This bulk-driven mixer exhibits a measured conversion gain of -1 plusmn 2 dB from 10 to 35 GHz of radio frequency (RF) with a fixed intermediate frequency (IF) of 100 MHz. The measured local oscillation (LO) to IF and RF-IF isolations are better than 30 dB. The chip area of the mixer is 0.6 times 0.4 mm². The total power consumption included output buffer is only 6 mW.     

Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell

This paper presents the first quadrature RF receiver front-end where, in a single stage, low-noise amplifier (LNA), mixer and voltage-controlled oscillator (VCO) share the same bias current. The new structure exploits the intrinsic mixing functionality of a classical LC tank oscillator providing a compact and low-power solution compatible with low-voltage technologies. A 0.13-mum CMOS prototype tailored to the GPS application is presented. The experimental results exhibit a noise figure of 4.8 dB, a gain of 36 dB, an IIP3 of -19 dBm with a total power consumption of only 5.4 mW from a voltage supply of 1.2 V