2.5Gb/s Ga As MESFET定时判决电路

设计了 2 .5 Gb/ s光纤通信用耗尽型 Ga As MESFET定时判决电路 .通过 SPICE模拟表明恢复的时钟频率达2 .5 GHz,判决电路传输速率达 2 .5 Gb/ s.实验证明经时钟信号抽样后判决电路可产生正确的数字信号 ,传输速率达 2 .5 Gb/ s     

InP基功率HEMT结构材料分子束外延生长研究

从 3个层面研究了分子束外延 Al0 .48In0 .52 As/ Ga0 .47In0 .53As/ In P功率 HEMT结构材料生长技术。首先 ,通过观察生长过程的高能电子衍射 (RHEED)图谱 ,确立了 Ga0 .47In0 .53As/ In P结构表面层的 MBE RHEED衍射工艺相图 ,据此生长的单层 Si-doped Ga0 .47In0 .53As(40 0 nm) / In P室温迁移率可达 6960 cm2 / V· s及电子浓度 1 .3 3 E1 7cm- 3。其次 ,经过优化结构参数 ,低噪声 Al0 .48In0 .52 As/ Ga0 .47In0 .53As/ In P HEMT结构材料的 Hall参数达到μ30 0 K≥ 1 0 0 0 0 cm2 / V· s、2 DEG≥ 2 .5 E1 2 cm- 2 。最后 ,在此基础之上 ,降低 spacer的厚度、在 Ga0 .47In0 .53As沟道内插入 Si平面掺杂层并增加势垒层的掺杂浓度获得了功率 Al0 .48In0 .52 As/ Ga0 .47In0 .53As/ In PHEMT结构材料 ,其 Hall参数达到μ30 0 K≥ 80 0 0 cm2 / V· s、2 DEG≥ 4 .0 E1 2 cm- 2 。     

2.5Gb/s GaAs MESFET定时判决电路

设计了2.5Gb/s光纤通信用耗尽型GaAs MESFET定时判决电路.通过SPICE模拟表明恢复的时钟频率达2.5GHz,判决电路传输速率达2.5Gb/s.实验证明经时钟信号抽样后判决电路可产生正确的数字信号,传输速率达2.5Gb/s.     

40Gb/s光纤通信系统中自适应判决反馈均衡器的补偿性能

数值仿真了40Gbit/s 非归零码(NRZ)光纤通信系统中,基于最小均方差算法的非线性自适应判决反馈均衡器对系统传输损伤的补偿性能.仿真结果表明,对于单信道40 Gbit/s NRZ系统,在同时考虑色散和自相位调制情况下,自适应判决反馈均衡器的引入可以使系统色散容限(1 dB眼图张开度代价)得到明显改善.在信号丢失率为10-3条件下,PMD容限由补偿前的0.17/单位比特周期,可提高到补偿后的0.22/单位比特周期.     

用GaAs MMIC实现2.1GHz的预失真线性化单片

介绍了一种预失真线性化单片电路,该电路单电源工作,采用预失真技术结合有源反馈的方法,完成了单片预失真线性化电路的研制.预失真线性化单片电路采用75 m m Ga As MMIC工艺研制,芯片面积约为4 mm2 .结果表明,2 .1GHz时此预失真单片电路可改善放大器的三阶互调分量9d B     

世界最快的光纤通信网

日本电信电话公司和庆应大学开始试验世界最快的光纤通信网 ,信息传输速度达 43Gbit/s。据预测 ,经过 1年试验确认其稳定性之后 ,将在2 0 0 5年建设连接研究所和大企业的超高速光通信网。此次试验所用光缆全长约 1 2 0km ,线路上的通信装置可监测传输信息时出现的错误并快速矫正 ,信息传输速度从原来的 1 0Gbit/s提高到43Gbit/s。试验时间计划持续到 2 0 0 4年 1 1月 ,预计于 2 0 0 5年 3月拿出稳定性数据。目前 ,速度最快的光纤通信网可同时传输 80种不同的信号 ,单波长信息的传输速度为 1 0Gbit/s。日本这次进行的单波长试验 ,43Gbit/s…     

10 Gbit/s 0.18 μm CMOS光纤通信用数据判决电路设计

介绍了采用TSMC公司 0.18 μm CMOS工艺设计速率为10 Gbit/s的数据判决电路,分析了数据判决电路的系统结构以及单元电路结构,给出了仿真结果.该电路采用 1.8 V电源供电,功耗为102 mW,50 Ω负载上单端输出摆幅400 mV.整个芯片面积为0.80 mm×1.05 mm.     

16.5～20GHz PHEMT单片功率放大器

采用南京电子器件研究所的 76 mm Ga As的 PHEMT单片技术 ,进行了 1 6 .5～ 2 0 GHz的 PHEMT MMIC的设计与研制。其中 PHEMT器件选用双平面掺杂 Al Ga As/In Ga As/Ga As PHEMT异质结结构 ,0 .5μm栅长的 76 mm Ga As工艺制作。在 MMIC设计中 ,准确的器件模型是设计 Ku波段单片的关键。为了保证单片研制的成功 ,利用 Agilent软件进行了 PHEMT器件模型的提取。模型可直接应用于 HP- EESOF Libra软件中 ,进行线性和非线性分析。PHEMT单片放大器采用三级有耗匹配放大器拓扑 ,输入和输出端口匹配至 50 Ω,CPW形式引…     

分子束外延生长高应变单量子阱激光器

采用分子束外延方法研究了高应变 In Ga As/Ga As量子阱的生长技术 .将 In Ga As/Ga As量子阱的室温光致发光波长拓展至 116 0 nm,其光致发光峰半峰宽只有 2 2 me V.研制出 112 0 nm室温连续工作的 In Ga As/Ga As单量子阱激光器 .对于 10 0 μm条宽和 80 0 μm腔长的激光器 ,最大线性输出功率达到 2 0 0 m W,斜率效率达到 0 .84m W/m A,最低阈值电流密度为 45 0 A/cm2 ,特征温度达到 90 K.     

用于光纤传输系统的10Gbit/s CMOS 1:8分接器

采用TSMC 0.25μm RF CMOS工艺设计了一个应用于光纤传输系统的10Gbit/s CMOS 1:8分接器.整个系统采用树型结构,由3级1:2分接器、2级1:2分频器、级间缓冲器和输入、输出接口电路构成.为了适应高速度的要求,所有电路全都采用源极耦合场效应管逻辑来实现.使用SmartSpice进行了仿真,结果表明:在电源电压为3.3V时,电路的最高工作速率可以达到10Gbit/s,电路功耗约为800mW.     

Applications of single and dual gate GaAs MESFETs for Gbit/s optical data transfer systems

Intrinsic large signal rise and fall times of less than 30 ps without charge storage demonstrate the potential of single and dual gate GaAs MESFETs for Gbit/s optical communication systems. The applications as signal regenerator, bit synchronizer, laser modulator, multiplexer, and demultiplexer are shown. Using only one dual gate GaAs MESFET clock and pulse shape regeneration as well as 1 Gbit/s laser modulation is performed. Bit synchronization is demonstrated up to 4 Gbit/s. 1 to 2 Gbit/s and 2 to 4 Gbit/s multiplexing as well as 2 to 1 Gbit/s demultiplexing with additional clock and pulse shape regeneration is shown using dual gate FETs. 2 to 4 Gbit/s multiplexing without clock regeneration is also accomplished using single gate GaAs MESFETs.     

光纤混沌双向保密通信系统研究

本文提出光纤混沌双向保密通信设想,通过耦合光注入半导体激光器激光混沌全光耦合反馈同步系统和光纤传输信道,建立了光纤混沌双向通信系统模型,数值实现了该系统在长距离光纤传输中的同步,详细地分析了系统同步时间随光纤传输长度的关系.证明了光纤的交叉相位调制是限制激光混沌在光纤传输中同步的主要原因,导出了系统传输的非线性相移.数值模拟了具有正弦调制信号的调制频率0.5GHz混沌模拟通信和数字信号调制速率0.4Gbit/s以及20Gbit/s的混沌数字通信以及调制速率0.05Gbit/s 混沌键控通信的应用,计算出光纤混沌数字通信速率和同步误差等关系,还特别分析了系统解码特性和调制带宽,表明系统具有非常好的保密性能和具有高速率通信的能力.光纤混沌双向保密通信是可以实现的.     

A 40-Gbit/s superdynamic decision IC fabricated with 0.12-μmGaAs MESFET's

This paper describes a 4O-Gbit/s decision integrated circuit (IC) fabricated with 0.12-μm gate length GaAs metal-semiconductor field-effect transistors (MESFET's). A superdynamic flip-flop circuit and a wide-band amplifier were applied in order to attain 40-Gbit/s operation. A conventional static decision IC was also fabricated for comparison. The dynamic decision IC operated up to 40 Gbit/s, which is twice as fast as the conventional static decision IC. Error-free 40-Gbit/s operation is the fastest among GaAs MESFET decision IC's     

AlGaAs/GaAs heterojunction bipolar transistor decision circuit

An AlGaAs/GaAs heterojunction bipolar transistor (HBT) decision circuit has been designed and characterised for optical communications, using 3.5 mu m emitter width transistors with cutoff frequency of 27 GHz. The maximum bitrate for a BER of 10/sup -9/ was 4.2 Gbit/s. At 2.0 Gbit/s, the clock phase margin was 240 degrees .<>     

Theoretical model of optical fiber secure communication system with chaotic multiple-quantum-well lasers

Chaotic synchronization of injected multiple-quantum-well lasers of optical fiber system and a theoretical model of optical fiber chaotic secure communication system are presented by coupling a chaotic multiple-quantum-well laser synchroniza- tion system and a fiber channel. A new chaotic encoding method of chaos phase shift keying On/Off is proposed for optical fiber secure communications. Chaotic synchronization is achieved numerically in long-haul fiber system at wavelength 1.55 μm. The effect of the nonlinear-phase of fiber is analyzed on chaotic signal and synchronization. A sinusoidal signal of 0.2 GHz frequency is simulated numerically with chaos masking in long-haul fiber analog communication at wavelength 1.55 μm while a digital signal of 0.5 Gbit/s bit rate is simulated numerically with c1haos masking and a rate of 0.05 Gbit/s are also simulated numerically with chaos shift keying and chaos phase shift keying On/Off in long-haul fiber digital communica- tions at wavelength 1.55 μm     

Fully monolithic integrated 43 Gbit/s clock and data recoverycircuit in InP HEMT technology

A fully monolithic integrated 43 Gbit/s clock and data recovery circuit for optical fibre communication systems is described. The circuit is based on a phase-locked loop technique, and the input data signal is regenerated with the data-rate clock signal. The circuit was fabricated with 0.1 μm gate-length InAlAs/InGaAs/InP HEMTs, and error-free operation was confirmed for 2³¹-1 PRBS data signal at 43 Gbit/s     

High-speed GaAs SCFL monolithic integrated decision circuit for Gbit/s optical repeaters

A high-speed GaAs monolithic integrated decision circuit for Gbit/s optical repeaters, based on source coupled FET logic (SCFL) and designed to be completely ECL-compatible, has been developed. A clock phase margin of 150 degrees at 2 Gbit/s and IC yields of about 60% are achieved by using SCFL configuration. The developed IC operates stably from 10 to 60°C ambient temperature over a supply voltage fluctuation of more than 2 V.     

2.5 Gbit/s码位重叠快跳频光码分多址实验系统

设计并实现了单用户、数据速率2.5 Gbit/s的码位重叠快跳频光码分多址(SO-FFH OCDMA)实验系统。采用波长数为7和码长为4的单重合码,在数据速率2.5 Gbit/s时设计和制作了基于光纤布拉格光栅(FBG)的光编码/解码器,并测试了光编码器和光解码器的频谱图。脉冲发生器产生2.5 Gbit/s的非归零(NRZ)脉冲信号,外调制放大自发辐射(ASE)宽带光源后,通过光环行器进入光编码器进行光信号的扩频编码。编码后的光信号经掺铒光纤放大器(EDFA)放大后,输入到光解码器进行扩频解码,并通过2.5 Gbit/s接收模块转换为电信号。从解码信号的波形看,在用户数据速率为2.5 Gbit/s时,该系统能够正确解码用户的数据信息。实验结果表明,相对于传统的快跳频光码分多址系统,码位重叠快跳频光码分多址可大大提高用户的数据速率。     

Low power data decision IC for 20-40 Gbit/s data links using 0.2μm AlGaAs/GaAs HEMTs

A decision IC for optical data links at bit rates of 20-40 Gbit/s has been realised by using 0.2 μm AlGaAs/GaAs HEMT technology and tested on-wafer at bit rates up to 25 Gbit/s. The IC can be operated with a supply from ~3.3 to 5.2 V and a DC current of ~50 mA