离子注入技术现状与发展趋势

离子注入制程已成为器件设计的最前端工作．现在更被视为实现32nm和22nm晶体管制程的推动要素。器件漏电流、浅结面制作，器件尺寸缩小，以及急速增加成本的挑战，正在限制摩尔定律的延伸。针对32nm节点离子注入制程器件的工艺要求．介绍了离子注入设备的发展方向。     

失效器件分析

As重掺杂Si片的电阻率可低到10-3 Ω·cm,可用作外延片的衬底材料,对于正向压降低的半导体器件来说,用这类外延片制作器件是最恰当的选择.As重掺杂Sj片在外延时容易产生气相自掺杂,尤其是同型外延时还存在固态外扩散现象,在整个制作器件过程中易产生工艺参数偏差,导致器件性能下降,严重时器件失效,当然衬底材料也可以选用价格较高的背处理工艺Si片,能有效地抑制由于后续加工工艺产生的许多缺陷.对某生产厂生产的一批器件电参数性能下降的原因进行了剖析,分析阐明了以As重掺杂Si片为衬底的外延片中衬底杂质对器件质量的影响.     

用离子注入工艺改善Si/SiGe HBT 高频噪声性能

常规工艺制作的SiGe/Si HBT高频噪声性能不理想的主要原因是其基极电阻较大,为减小基极电阻从而达到改善其高频噪声的目的,本文采用离子注入自对准工艺方法进行器件制作,并测试出器件的直流与最小噪声系数有显著改善.     

不同工艺制备的GaAs MESFET阈值电压均匀性研究

分别采用离子注入隔离凹栅工艺、自隔离平面工艺、离子注入隔离平面工艺在非掺杂半绝缘 Ga As衬底上制备 MESFET,对三种工艺制备的 MESFET的阈值电压均匀性进行了研究。结果表明 ,器件工艺对 MESFET阈值电压有一定的影响 ,开展 Ga As MESFET阈值电压均匀性研究应采用适宜的工艺 ,以尽可能减少工艺引起的偏差。     

InP/Si键合技术研究进展

InP材料及其器件的研制是近年来研究热点之一,而键合技术又是光电子集成研究领域内一项新的制作工艺。利用键合技术结合离子注入技术可以InP薄膜及器件集成到Si衬底上,改善机械强度,降低成本,具有非常诱人的应用前景。概括地介绍了近年来InP在Si上的键合工艺及层转移技术研究进展,并对InP和Si的几种键合工艺进行了分析。降低InP和Si键合温度,进行低温键合是其发展趋势。比较几种键合技术,利用等离子活化辅助键合是降低键合温度的有效途径。     

980nm半导体激光器长期老化结果及失效分析

为了提高980nm半导体激光器的可靠性,采用氦离子注入形成腔面电流非注入区技术制作了4μm条宽的脊形波导激光器,并利用同一块外延片制作了常规工艺的4μm脊形波导激光器作为对比。经过长期老化实验得知:常规工艺器件在1500h前全部失效,而采取新技术的器件寿命超过了3000h。通过对器件的扫描电镜分析发现,腔面灾变性损伤、铟焊料的质量和腔面污染等因素对器件失效有直接影响。     

用248nm光刻机制作150nm GaAs PHEMT器件性能及可靠性评估

介绍了基于光刻机的150 nm T型栅Ga As PHEMT工艺,其中重点介绍了使用的shrink关键工艺步骤。利用新工艺在某100 mm Ga As工艺线上进行流片,并通过直流测试、loadpull测试、微波小信号测试以及环境试验、极限电压测试、高温步进试验,获得新工艺下制作的Ga As PHEMT的各项性能指标及可靠性。最后制作得到的器件在性能和通过直接光刻得到的PHEMT在性能和可靠性上基本在一个水平上,但是想要通过shrink工艺得到线宽更细的栅长需要进一步努力。     

过腐蚀自对准离子注入法制备SiGe HBT

用过腐蚀自对准离子注入工艺制备SiGe/Si异质结双极型晶体管，过腐蚀湿法腐蚀的横向钻蚀，为自对准离子注入提供了技术保障. 对外基区的离子注入既减小了外基区的串联电阻，又有利于欧姆接触的制备，提高了器件的工艺成品率.     

低温硅结合离子注入技术制备应变Si材料

为制作应变硅MOS器件,给出了一种制备具有高表面质量和超薄SiGe虚拟衬底应变Si材料的方法。通过在Si缓冲层与赝晶Si0.8Ge0.2之间设置低温硅（LT-Si）层,由于失配位错限制在LT-Si层中且抑制线位错穿透到Si0.8Ge0.2层,使表面粗糙度均方根值（RMS）为1.02nm,缺陷密度系106cm-2。又经过P+注入和快速热退火,使Si0.8Ge0.2层的应变弛豫度从85.09%增加到96.41%,且弛豫更加均匀。同时,RMS（1.1nm）改变较小,缺陷密度基本没变。由实验结果可见,采用LT-Si层与离子注入相结合的方法,可以制备出满足高性能器件要求的具有高弛豫度、超薄SiGe虚拟衬底的高质量应变Si材料。     

过腐蚀自对准离子注入法制备SiGe HBT

用过腐蚀自对准离子注入工艺制备SiGe/Si异质结双极型晶体管,过腐蚀湿法腐蚀的横向钻蚀,为自对准离子注入提供了技术保障.对外基区的离子注入既减小了外基区的串联电阻,又有利于欧姆接触的制备,提高了器件的工艺成品率.     

Multi-wafer growth of highly uniform InGaP/GaAs by low pressure MOVPE

This paper reports on the large area growth of InGaP/GaAs heterostructures for short wavelength applications (λ ∼ 650 nm) by low pressure MOVPE in a vertical, high speed, rotating disk reactor. Highly uniform films were obtained both on a single 50 mm diam wafer at the center of a 5 inch diam wafer platter and on three, 50 mm diameter GaAs wafers symmetrically placed on a 5 inch diam platter. Characterization was performed by x-ray diffraction, SEM, and room temperature photoluminescence (PL) mapping. For the single wafer growth, PL mapping results show that the total range on wavelength was ±2 nm with a 2 mm edge exclusion. The standard deviation of the peak wavelength,σ _w , is 0.7 nm. Thickness uniformity, measured by SEM, is less than 2%. Similar results were obtained for the multi-wafer runs. Each individual wafer has aσ _w of 1.1 nm. The wafers have nearly identical PL maps with the variation of the average wavelength from the three wafers within ±0.1 nm.     

全自动反应离子腐蚀3英寸GaAs片实验研究

介绍了全自动反应离子腐蚀３英寸ＧａＡｓ片的实验研究工作。实验获得良好结果，均匀性约５％，２０分钟腐蚀深度为２０μｍ。     

Ka-band monolithic amplifier using 0.5 mu m gate length ion-implanted GaAs/AlGaAs heterojunction FET technology

Monolithic, two-stage amplifiers using 0.5*80 mu m/sup 2/ gate GaAs/AlGaAs heterojunction FETs have been developed for Ka-band operation. These monolithic two-stage amplifiers were fabricated using ion implantation for the active layer and optical lithography for the 0.5 mu m gate length. MMIC two-stage amplifiers achieved average gains of 12.6+or-1.4 dB at 30 GHz and 8.8+or-2.0 dB at 40 GHz, respectively, for all 39 sites across a three inch diameter wafer. These are the first reported results for MMIC two-stage amplifiers using 0.5 mu m gate length ion-implanted GaAs/AlGaAs heterojunction FETs achieving over 10 dB gain at Ka band.<>     

Wafer reuse for repeated growth of III–V solar cells

The epitaxial lift‐off (ELO) technique can be used to separate a III–V solar cell structure from its underlying GaAs or Ge substrate. ELO from 4‐inch Ge wafers is shown and 2‐inch GaAs wafer reuse after lift‐off is demonstrated without degradation in performance of the subsequent thin‐film GaAs solar cells that were retrieved from it. Since a basic wet chemical smoothing etch procedure appeared insufficient to remove all the surface contamination, wafer re‐preparation is done by a chemo‐mechanical polishing procedure. Copyright © 2010 John Wiley & Sons, Ltd.     

GaAs PIN二极管大功率毫米波单刀双掷开关单片

采用76.2mm(3英寸)GaAs PIN二极管工艺设计和制作了大功率毫米波单刀双掷开关单片。采用并联结构的单刀双掷开关以获得较高的功率特性。在片测试表明,在30～36GHz工作频段,开关导通支路插损1.0dB,驻波优于1.5,开关关断端口隔离度大于34dB。开关在导通态下输入功率0.5dB压缩点P-0.5 dB大于5W。     

兆声清洗在GaAs PHEMT栅凹槽工艺中的应用

对GaAs赝配高电子迁移率晶体管(PHEMT)在栅凹槽光刻和栅凹槽腐蚀过程中光刻窗口内经常出现的一些沾污颗粒进行了分析.设计了一系列实验来分析残留在芯片上的颗粒度参数,采用4英寸(1英寸=2.54 cm)圆片模拟实际的栅凹槽清洗工艺过程,利用颗粒度测试仪分别测试了4英寸圆片表面不同粒径的沾污颗粒数在喷淋和兆声清洗两种条件下的变化情况.比较两种清洗结果,兆声清洗方法可以有效去除栅凹槽颗粒沾污.在实际流片过程中,采用兆声清洗方法大幅降低了源漏间沟道漏电数值,同时芯片的直流参数成品率由之前的75％提高到了93％.     

TCAD simulation of ion implantation test for controlling quality of GaAs substrates used for fabricating implanted devices

The quality of GaAs substrate material for manufacturing ion implanted devices is routinely determined by an ion implantation test. The test involves measuring an electrical quantity, such as sheet resistance, after implanting Si into the substrate. This work employs GaAs TCAD simulation to address the range of validity of the implantation test and the pitfalls associated with it. The results show that the electrical measurements are capable of discerning typical variation in the carbon concentration in the substrate. But, the surface or interface charge on GaAs, which may result from processing involved in wafer preparation, is also important. Therefore, while the implantation test in most cases is adequate to control the quality of the substrate, the test is susceptible to misinterpretation owing to the variations arising from the process involved in wafer preparation for the test.     

基于硼酸溶液处理的GaAs/InP低温晶片键合技术

提出了一种基于硼酸溶液的GaAs/InP低温晶片键合技术,实现了GaAs/InP基材料间简单、无毒性的高质量、低温(290℃)晶片键合。GaAs/InP键合晶片解理截面的扫描电子显微镜(SEM)图显示,键合界面整齐,没有裂缝和气泡。通过键合过程,InP上的In0.53Ga0.47As/InP多量子阱结构转移到了GaAs基底上。X射线衍射及荧光谱显示,键合后的多量子阱晶体质量未变。二次离子质谱(SIMS)和Raman光谱图显示,GaAs/InP键合晶片的中间层厚度约为17 nm,界面处B元素有较高的浓度,键合晶片的中间层很薄,因此可以得到较好的电学、光学特性。     

Comparison of GaAs grown on standard Si (511) and compliant SOI (511)

Gallium arsenide (GaAs) films were grown by molecular beam epitaxy (MBE) on a (511) silicon substrate and a compliant (511) silicon-on-insulator (SOI) substrate. The top silicon layer of the compliant (511) SOI was thinned to ～1000 Å. The five inch diameter SOI wafer was created by wafer bonding. The GaAs (004) x-ray diffraction (XRD) reflection showed a 25% reduction in the full width half maximum (FWHM) for GaAs on a compliant (511) SOI as compared to GaAs on a silicon substrate. Cross section transmission electron microscopy (XTEM) clearly indicates a different dislocation structure for the two substrates. The threading dislocation density is reduced by at least an order of magnitude in the compliant (511) SOI as compared to the (511) silicon. XTEM found dislocations and damage was generated in the top silicon layer of the compliant SOI substrate after GaAs growth.     

SZ541和SZ551型GaAs高速分频器

本文叙述了SZ541和SZ551分频器工作原理、电路设计和制作工艺技术。电路采用全离子注入平面工艺,L_g为0.6～0.8μm.SZ541GaAs静态分频器可从DC到3GHz工作。SZ551GaAs动态分频器工作带宽为0.5～4.5GHz。