半导体器件建模与优化系统

随着器件尺寸的缩小,器件特性空间变得越来越复杂.如果仍采用手工参数调整的方法,不仅需要有较好的器件物理知识,而且也不一定能得到合适的结果.为节约设计时间,对半导体器件建模与优化系统(MOSSED)进行了研究与实现.该系统可以对半导体器件进行有效地建模、优化和综合,以得到所需要的器件.通过一些实例对部分功能进行了说明,并和一些已有的系统进行了比较.     

半导体保护器件阴极短路区的设计

为改善半导体保护器件的主要特性参数,通过对半导体保护器件基本原理的简单论述,深入研究了阴极短路结构的相关理论,分析了阴极短路区结构和工艺对半导体保护器件主要特性参数的影响,提出了优化半导体保护器件主要特性参数的一些方法。     

基于马尔科夫过程的半导体激光器空间辐射可靠性分析

通过对半导体激光器辐射效应的分析,得到了器件在空间环境中的损伤规律和退火规律.根据辐射效应的特点,将器件的性能退化表示为泊松过程与指数过程的结合,建立了基于马尔科夫过程的可靠性模型,利用一步概率转移矩阵获得了故障概率分布函数、可靠度函数以及平均故障前时间的计算方式.根据已有数据,对半导体激光器在空间辐射环境中的性能退化过程进行了仿真,得到了总测试时间为100 000 h时器件的故障概率分布曲线,计算得出平均故障前时间约为42 758.9 h,此时器件可靠度为0.451.分析了不同时间条件下器件的状态概率分布律,结果符合器件性能退化的一般规律,能够描述出器件的失效过程.     

半导体分立器件断腿分析

本文对半导体分立器件的断腿问题作了一些分析,对断腿产生的原因及清除缺陷的途径提出了一些见解.     

半导体生产规划中的优化决策方法:线性规划

半导体制造是一个流程高度复杂,资金高度密集的加工过程,相对于其它制造业来说,其产品种类繁多,工序复杂,对设备的利用率要求较高,因而生产优化也较为复杂.本文利用线性规划(linear programming,LP),对半导体制造的封装和测试过程进行数学建模,并构建一套决策支持系统.与电子表格手工计算相比,该系统大大缩短了生产计划响应时间,并提高了瓶颈设备利用率.     

新型匹配负载网络的TLP测试系统研究

研究了传统传输线脉冲测试波形的失真机理,实现了一种基于R-2R网络的负载电路匹配特性优化设计方案,与传统传输线脉冲测试波形相比,优化之后的系统消除了传统设备所产生脉冲波形的过冲和振荡现象.从而提高了传输线脉冲测试效率.同时,在相同的预充电电压下,优化之后的系统能提供更大能量的测试脉冲,减小系统功耗.该工作对半导体器件的ESD保护电路设计和ESD模型研究具有实用价值.     

全双工直接调制激光器光网络单元的优化研究

光放大器是光通信的关键组成部分。对半导体光放大器的算法模型进行优化与测试,系统的分析了建模运放的增益和噪声指数。测试结果表明,半导体光放大器的最佳幅度调制条件是输入-5dBm的功率与选择100mA的偏置电流,最佳相位调制条件是输入-20dBm的功率与选择100mA的偏置电流。分析并搭建了通信速率为2.5 Gb/s的20km双向传输通信系统,对半导体光放大器和分布反馈激光器集成的光网络单元进行了上行链路和下行链路的双向与单向传输测试。在前向误码率要求为2.4×10-4时,双向传输的上行接收灵敏度达到 -22.4dBm,下行接收灵敏度达到 -31.4dBm;单向传输的上行下行接收灵敏度分别达到 -22.7dBm 和-31.6dBm。     

MAXIIZ令CPLD在便携式应用大展拳脚

Altera公司近日宣布推出其MA-Ⅻ系列CPLD产品的新版本--零功耗MAX(R)IIZ,该器件专门为便携式应用市场而开发,其功耗、封装和价格相比以往版本都得到大幅优化. 便携式电子产品设计要求呈现出的主要特点是,集成越来越多功能,同时功耗越来越低;产品生命周期缩短;个性化设计突出.对半导体解决方案的要求就是尺寸小、功耗低、成本低,同时设计灵活性高.MAXIIZ针对这些方面做了专门优化.     

对硅器件工艺诱生热缺陷的一种无损检测技术——XCD-H红外电视测微显微镜的应用研究

对半导体硅及其器件芯片中的诱生热缺陷,用XCD-H红外电视显微镜进行了无损检测.通过显微拍照和磁带录相,获得了电活性位错与堆垛层错微区金属杂质富集以及氧沉淀环状活性团等清晰的红外透视图象.结果表明,该种红外透视的系统能够提供相当重要的信息,因而将对器件工艺的质量分析,进一步提高芯片的内在质量产生有益的影响.     

基于Petri网与遗传算法的半导体生产线建模与优化调度

针对半导体生产线调度复杂、难以优化的问题,本文提出了一种基于层次有色赋时Petri网技术和遗传算法相结合的优化调度方法。该方法利用层次化的方法结合自顶向下建模方法对半导体生产线进行模块化建模,模型不仅能够反映生产线的待加工产品的多条加工路径及其资源约束,还可以对系统的设备维护、各种优先级等特性进行描述,得到对生产系统更完善更精确的刻画。通过在遗传算法编码中同时考虑投料策略、工件选设备规则、批加工调度规则和单件加工设备规则等因素得到更加有效的调度方案,提高了模型的优化程度。在此基础上,对实际半导体生产线的不同调度方案分别进行了仿真,并对仿真结果进行了比较,从而验证了建模方法的正确性及调度策略的有效性。     

High-power robust semiconductor electronics technologies in the new millennium

This paper presents an overview of power semiconductor devices for the development of advanced robust high-performance power electronic systems for the new millennium. Material and device technologies on silicon and wide energy band-gap semiconductors are discussed along with switching circuits and topologies. Short-term and long-term reliability issues of power semiconductor devices are discussed. An approach is presented to correlate converter field failures to dynamic switching stresses, residual defects and contaminants left in the semiconductor power switch, packaging, and thermal management. Component and system level simulation, modeling and CAD requirements are evaluated. System-level optimization is proposed as an essential requirement to develop robust power systems at affordable cost.     

Steady-state and dynamic thermal models for heat flow analysis of silicon-on-insulator MOSFETs

Self-heating in silicon-on-insulator (SOI) MOSFETs has become one of the vital issues for design, characterization, optimization and reliability prediction of SOI devices and integrated circuits due to the low thermal conductive buried oxide (BOX) and the continual increase in the microelectronic packaging density. Thermal models that are accurate and detailed enough to provide device temperature profiles and efficient enough for large scale electro-thermal simulation are therefore strongly desirable. This paper discusses the fundamental concepts for modeling of heat flow in semiconductor devices. A brief overview for the conventional approaches to thermal modeling of the SOI devices is given. Improved steady-state and dynamic SOI heat flow models based on the SOI film thermal resistance for efficient prediction of steady-state and dynamic temperature variations in SOI devices are presented. These improved models are applied to investigate temperature distributions and temporal evolution of the junction temperature in SOI nMOSFETs.     

Status and application of HgCdTe device modeling

In this article, device modeling refers to numerical simulation of semiconductor device physics to predict electrical behavior. The silicon integrated circuit industry provides the example for the use of technology computer-aided design to simulate wafer fabrication processes, and the electrical performance of devices and circuits. This paper first reviews semiconductor device modeling in general, then as applied in work supporting the development and analysis of HgCdTe infrared detectors. Example applications of one- and two-dimensional device modeling are simulation of a bias-selectable, integrated two-color detector, and two-dimensional effects on the spectral response of a HgCdTe detector with composition grading.     

Finite-element modeling predicts possibility of thermoelectrically cooled lead-salt diode lasers

Finite-element thermal modeling shows that thermoelectric cooled operation of IV-VI semiconductor diode lasers is possible by replacing the thermally resistive lead-salt substrate with copper. Contrasting thermal models reveal a 63 K decrease in active region temperature under normal operating conditions when PbTe is replaced with copper. This improved device structure can be obtained by using epitaxial-lift-off techniques similar to those developed for III-V semiconductor devices.     

Capacitance of semiconductor p-n junction space-charge layers: anoverview

The modeling of capacitance of p-n junction space-charge layers in semiconductor devices is discussed. First, previously developed models and methods are reviewed. Capacitance models developed recently by the authors that include mobile-carrier, nonquasi static, and multidimensional effects are then considered. These models yield more accurate device and circuit simulations for semiconductor integrated circuits. The emphasis is on diodes and bipolar transistors, but many concepts used apply as well to p-n junctions of metal-oxide-semiconductor field effect transistors. The review includes conventional homojunction devices (devices fabricated with a single semiconductor such as silicon) and the increasingly important heterojunction devices (devices fabricated with two or more semiconductors or a semiconductor having a spatially varying chemical composition such as gallium-aluminum-arsenide)     

Electro-thermal analysis and optimization of edge termination of power diode supported by 2D numerical modeling and simulation

High reliability and performance of power semiconductor devices depend on an optimized design based on a good understanding of their electro-thermal behavior and of the influence of parasitic components on their operation. This leads to the need for electro-thermal 2/3-D numerical modeling and simulation in power electronics as an efficient tool for analysis and optimization of device structure design and identification of critical regions. In this paper we present an analysis and geometry optimization of a high power pin diode structure supported by advanced 2-D mixed mode electro-thermal device and circuit simulation. Lowering of the operation temperature by better power management and heat dissipation due to an optimized structure design will allow withstanding higher current pulses and suppressing the damage of the analyzed structure by thermal breakdown.     

A compact charge-based model to study the nanoscale undoped double gate MOSFETs for nanoelectronic circuit design using genetic algorithms

The analytical modeling of nanoscale devices is an important area of computer-aided design for fast and accurate nanoelectronic design and optimization.In the present paper,a new approach for modeling semiconductor devices,nanoscale double gate DG MOSFETs,by use of the gradual channel approximation(GC) approach and genetic algorithm optimization technique(GA) is presented.The proposed approach combines the universal optimization and fitting capability of GA and the cost-effective optimization concept of quantum correction,to achieve reliable,accurate and simple compact models for nanoelectronic circuit simulations.Our compact models give good predictions of the quantum capacitance,threshold voltage shift,quantum inversion charge density and drain current.These models have been verified with 2D self-consistent results from numerical calculations of the coupled Poisson-Schrodinger equations.The developed models can also be incorporated into nanoelectronic circuit simulators to study the nanoscale CMOS-based devices without impact on the computational time and data storage.     

Electrical overstress and electrostatic discharge

Semiconductor devices have a limited ability to sustain electrical overstress (EOS). The device susceptibility to EOS increases as the device is scaled down to submicron feature size. At present, EOS is a major cause for IC failures. Published reports indicate that nearly 40% of IC failures can be attributed to EOS events. Hence, EOS threats must be considered early in the design process. For semiconductor devices, EOS embodies a broad range of electrical threats due to electromagnetic pulses, electrostatic discharge (ESD), system transients, and lightning. EOS-related failures in semiconductor devices can be classified according to their primary failure mechanisms into: thermally-induced failures, electromigration, electric-field-related failures. In general, thermally-induced failures are related to the doping level, junction depth, and device characteristic-dimensions whereas electric-field induced failures are primarily related to the breakdown of thin oxides in MOS devices     

DOE/Opt: a system for design of experiments, response surfacemodeling, and optimization using process and device simulation

Rapid modeling and optimization of manufacturing processes, devices, and circuits are required to support modern integrated circuit technology development and yield improvement. We have prototyped and applied an integrated system, called DOE/Opt, for performing Design of Experiments (DOE), Response Surface Modeling (RSM), and Optimization (Opt). The system to be modeled and optimized can be either physical or simulation based. Within the DOE/Opt system, coupling to external simulation or experimental tools is achieved via an embedded extension language based on Tcl. The external problem then appears to DOE/Opt as a model with user defined inputs and outputs. DOE/Opt is used to generate splits for experiments, to dynamically build and evaluate regression models from experimental runs, and to perform nonlinear constrained optimizations using either regression models or embedded executions. The intermediate regression modeling can appreciably accelerate the optimization task when simulation or physical experiments are expensive. The primary application of DOE/Opt has been to process optimization using coupled process and device simulation. DOE/Opt has also been applied to process and device simulator tuning, and to aid in device characterization. Such a DOE/Opt system is expected to augment the use of TCAD tools and to utilize data collected by CIM systems in support of process synthesis. We have demonstrated the application of the system to process parameter determination, simulator tuning, process control modeling, and statistical process optimization. We are extending the system to more fully support emerging device design and process synthesis methodologies     

遗传算法在半导体器件参数提取软件中的实现

随着半导体器件参数的增加,目标函数的自变量空间维数变得越来越大。传统的优化算法已经不能很好地处理此类问题,主要表现在无法有效地达到目标函数的极小点。文章首先在参数提取软件中实现了遗传算法,并与传统的优化算法进行了比较,探讨了该算法在参数提取软件中的实用性,提出了将遗传算法与传统优化算法结合在一起的方法。