共查询到19条相似文献,搜索用时 109 毫秒
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本文提出了在提取时序电路逻辑参数时,应用于SPICE模拟时的激励波形自动生成算法,该算法可以根据用户指定的各种相关参数进行激励波形的自动生成,从而缩短了建立逻辑参数库的时间. 相似文献
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逻辑参数库中Power参数的提取 总被引:1,自引:0,他引:1
本文介绍了在LPE这个逻辑参数(电学参数)自动提取工具里,Power参数的定义以及提取Power的输入激励波形的生成算法。对于不同的Related Pin以及电路的反馈特性需要不同的激励波形生成算法。 相似文献
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提出了一种标准单元工艺参数自动提取工具的实现方法。该工具能利用用户所提供的功能文件自动生成模拟所需的SPICE激励波形,并能根据SPICE激励波形自动进行参数提取,最后自动生成Synopsys综合库,Verilog仿真库和Vital仿++真库。该工具不仅可用于单个电路的工艺参数提取。也可应用于建立工艺参数库。工具缩短了建立工艺参数库的时间,也减少了工艺参数提取过程中人为引入的误差。 相似文献
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为减小现场可编程门阵列(FPGA)关键路径的延时误差,提出一种基于时延配置表的静态时序分析算法。算法建立了一种基于单元延时与互连线延时配置表的时延模型。该模型考虑了工艺角变化对延时参数的影响,同时在时序分析过程中,通过分析路径始节点与终节点的时钟关系,实现了复杂多时钟域下的路径搜索与延时计算。实验结果表明,与公认的基于查找表的项目评估技术(PERT)算法和VTR算法相比,关键路径延时的相对误差平均减少了8.58%和6.32%,而运行时间平均仅增加了19.96%和9.59%。 相似文献
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激光雷达脉冲回波的波形分解方法是提取其波形参数的重要手段,也为反演目标高度、倾斜度和粗糙度、反射率提供直接的参数来源。针对部分信噪比较差且具有一定混叠程度的脉冲回波,提出一种基于可变分量的参数随机抽样方法的波形分解算法(WDVCM)。该算法以高斯混合函数为优化模型,通过随机产生高斯分量的特征参数以及删减或生成高斯分量等操作,并分别基于能量函数和拟合标准差作为参数优化的判据,从而实现波形的分解及其参数提取。利用该算法对美国国家航空航天局(NASA)的对地观测星载激光雷达(GLAS)一个条带中的4584个原始波形进行了处理分析。结果发现,约99%的WDVCM和97%的NASA拟合波形结果的相关系数均超过0.95,其中两者相关系数差异不超过0.05占98%。同时,WDVCM和NASA拟合波形的标准差系数均值分别为2.21和3.28,约89%的WDVCM拟合波形的标准差系数均小于NASA拟合波形的标准差系数。所得结果表明,WDVCM对混叠高斯波形的拟合效果更好,适用性更强。 相似文献
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一类时序逻辑电路的逻辑参数提取激励波形自动生成 总被引:2,自引:0,他引:2
提出了对具有反馈信息的时序逻辑电路进行逻辑参数提取时用于 SPICE模拟的激励波形自动生成方法 ,该方法能根据用户指定的要提取的时延参数要求 ,很快产生这种时序逻辑电路的模拟激励波形 ,从而可以加快逻辑参数的提取过程 ,保证参数提取激励波形的正确性 .该方法的实现 ,可以使逻辑参数的提取完全自动化 ,缩短了逻辑参数库的建立时间 ,具有较高的适用价值 相似文献
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提出了对具有反馈信息的时序逻辑电路进行逻辑参数提取时用于SPICE模拟的激励波形自动生成方法,该方法能根据用户指定的要提取的时延参数要求,很快产生这种时序逻辑电路的模拟激励波形,从而可以加快逻辑参数的提取过程,保证参数提取激励波形的正确性.该方法的实现,可以使逻辑参数的提取完全自动化,缩短了逻辑参数库的建立时间,具有较高的适用价值. 相似文献
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全波形星载激光测高仪的接收波形特征参数可以用于反演目标的形貌信息,传统的波形处理算法不能用于混叠严重以及偏离高斯形态的多模式波形特征参数提取。针对混叠严重的多模式回波,提出一种基于偏正态拟合模型,使用激励Richardson-Lucy反卷积算法、逐层分解算法、梯度下降法和非线性最小二乘拟合算法相组合的波形特征参数提取方法。采用已知参数的波形数据集、机载仿真波形数据集和全球生态系统动态调查(GEDI)激光雷达波形数据,基于波形相关系数与均方根误差(RMSE)、波形特征参数相对误差、波形分量个数提取正确率等评价指标开展波形处理试验,并将处理结果与传统的高斯分解结果进行比较分析。已知参数波形数据集处理结果的平均波形相关系数提升了约2%,RMSE降低了约47%,波形特征参数相对误差平均降低了约5%,分量个数提取正确率提升了约34%;机载仿真数据和GEDI波形数据处理结果的平均波形相关系数分别提升了约1%和2%,RMSE分别降低了约56%和54%。同时,开展了陡坡区域植被高度解算的仿真试验,得到的植被高度准确程度明显高于传统方法。所有处理结果均表明该方法更有利于多模式回波特征参数的提取以及目标参数的反演。 相似文献
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LIUXin XIONGYou-lun 《中国电子科技》2005,3(2):134-139
This paper presents modeling tools based on Boolean satisfiability (SAT) to solve problems of test generation for combinational circuits. It exploits an added layer to maintain circuit-related information and value justification relations to a generic SAT algorithm. It dovetails binary decision graphs (BDD) and SAT techniques to improve the efficiency of automatic test pattern generation (ATPG). More specifically, it first exploits inexpensive reconvergent fanout analysis of circuit to gather information on the local signal correlation by using BDD learning, then uses the above learned information to restrict and focus the overall search space of SAT-based ATPG. Its learning technique is effective and lightweight. The experimental results demonstrate the effectiveness of the approach. 相似文献
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Delay testing is used to detect timing errors in a digital circuit.In this paper, we report a tool called MODET forautomatic test generation for path delay faults in modular combinational circuits. Our technique usesprecomputed robust delay tests for individual modules to computerobust delay tests for the module-level circuit. We present alongest path theorem at the module level ofabstraction which specifies the requirements for path selectionduring delay testing. Based on this theorem, we propose a pathselection procedure in module-level circuits and report efficientalgorithms for delay test generation. MODET hasbeen tested against a number of hierarchical circuits with impressivespeedups in relation to gate-level test generation. 相似文献
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Bose S. Agrawal P. Agrawal V.D. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1998,6(2):323-331
Current test generation algorithms for path delay faults assume a variable-clock methodology for test application. Two-vector test sequences assume that the combinational logic reaches a steady state following the first vector before the second vector is applied. While such tests may be acceptable for combinational circuits, their use for nonscan sequential circuit testing is impractical. A rated-clock path delay simulator shows a large drop in coverage for vectors obtained from existing test generators that assume a variable clock. A new test generation algorithm provides valid tests for uniform rated-clock test application. In this algorithm, signals are represented for three-vector sequences. The test generation procedure activates a target path from input to output using the three-vector algebra. For an effective backward justification, we derive an optimal 41-valued algebra. This is the first time, rated-clock tests for large circuits are obtained. Results for ISCAS-89 benchmarks show that rated-clock tests cover some longest, or close to longest, paths 相似文献
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This paper presents a new algorithm (PMS-BDD) based on the binary decision diagram (BDD) for reliability analysis of phased-mission systems (PMS). PMS-BDD uses phase algebra to deal with the dependence across the phases, and a new BDD operation to incorporate the phase algebra. Due to the nature of the BDD, cancellation of common components among the phases can be combined with the BDD generation, without additional operations; and the sum of disjoint products (SDP) can be implicitly represented by the final BDD. Several examples and experiments show that PMS-BDD is more efficient than the algorithm based on SDP, in both computation time and storage space; this efficiency allows the study of some practical, large phased-mission systems 相似文献
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本文提出了一种结合二叉判决图BDD和布尔可满足性SAT的新颖组合电路等价性验证技术.算法是在与/非图AIG中进行推理,并交替使用BDD扩展和基于电路SAT解算器简化电路.如尚未解决,将用基于合取范式SAT解算器进行推理.与已有算法相比主要有如下改进:在AIG中结合多种引擎进行简化,不存在误判可能;充分利用了基于电路解算器和基于合取范式解算器各自优点,减小了SAT推理的搜索空间.实验结果表明了本算法的有效性. 相似文献
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On broad-side delay test 总被引:1,自引:0,他引:1
Savir J. Patil S. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1994,2(3):368-372
A broad-side delay test is a form of a scan-based delay test, where the first vector of the pair is scanned into the chain, and the second vector of the pair is the combinational circuit's response to this first vector. This delay test form is called “broad-side” since the second vector of the delay test pair is provided in a broad-side fashion, namely through the logic. This paper concentrates on generation of broadside delay test vectors; shows the results of experiments conducted on the ISCAS sequential benchmarks, and discusses some concerns of the broad-side delay test strategy 相似文献
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Shelar R.S. Sapatnekar S.S. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(8):957-970
We address the problem of synthesizing pass transistor logic (PTL), with the specific objective of delay reduction, through binary decision diagram (BDD) decomposition. The decomposition is performed by mapping the BDD to a network flow graph, and then applying the max-flow min-cut technique to bipartition the BDD optimally under a cost function that measures the delay and area of the decomposed implementations. Experimental results obtained by running our algorithm on the set of ISCAS'85 benchmarks show a 31% improvement in delay and a 30% improvement in area, on an average, as compared to static CMOS implementations for XOR intensive circuits, while in case of arithmetic logic unit and control circuits that are NAND intensive, improvements over static CMOS are small and inconsistent. 相似文献