电镀铜粉产生原因分析及验证

电镀铜粉严重影响电路板的品质,其偶发性非常难以监测。而铜粉的产生对产品的可靠性有着致命的影响,其形成过程也曾困扰了很多优秀的工程师。本文从沉铜和电镀流程中铜粉产生的过程进行分析,论述了从沉铜到全板电镀加工过程中铜粉产生的几种原因,并通过实验验证了铜粉产生的原因。     

填孔电镀盲孔微蚀分界线成因浅析

随着PCB的轻、薄、小及高密互连的发展趋势,电镀铜填孔工艺已得到了广泛的应用,同时也伴随产生一些普通电镀未有之现象,本文主要介绍其中的一种,填孔电镀盲孔切片中孔内分界线的形成原因。     

图形电镀孔内无铜的产生原因分析

介绍了造成印制电路板图形电镀工艺过程中,孔内无铜产生的原因,根据流程分析给出了改善此缺陷的方向。     

镀通孔制造过程中的失效机理与物理模型

镀通孔的可靠性与制造过程工艺参数有非常密切的关系。从钻孔、化学镀铜、电镀三个主要工艺入手,对目前制造过程镀通孔失效的机理与物理模型的研究现状进行总结。重点介绍了钻孔中分层、化学镀铜中的气泡缺陷、电镀中的镀层不均匀等缺陷产生的机理。并提出了需进一步研究的主要问题。     

PCB图形电镀工艺的探索

随着电路板朝高集成度及高精密的方向日益发展，对其电镀铜工艺提出更高的要求。必须从电镀工艺特点进行改善和创新，提高制程能力，获得满足其性能的镀层：本文重点研究了PCB图形电镀的特点，对其常见品质异常进行分析，并提出解决方案：     

孔金属化电镀工艺技术与品质管控

文章介绍了PTH、电镀一铜（镀通孔,孔金属化）工艺技术与品质管控应该关注的重点,并结合相关药水介绍了工艺和操作层面应注意的一些问题。     

填孔电镀品质可靠性的研究和探讨

填孔电镀是满足PCB高密度化、更小化、更便宜的一种重要途径,随着电子行业和PCB行业的高速发展,填孔电镀的需求量增长迅速,填孔电镀的应用也日广泛,填孔电镀的生产难度也相应增加。填孔电镀是一种新工艺流程,相对普通电镀铜而言,其反应机理复杂,过程控制更难监控,品质可靠性低。本文主要讲述填孔电镀反应机理,并通过DOE试验来探讨如何提升填孔电镀工艺能力和品质可靠性。     

Neopact直接电镀工艺的应用

本文叙述了Neopact直接电镀工艺的应用,包括工艺过程及控制、各参数对溶液性能的影响、品质检验、废水处理等。该工艺稳定可靠、控制容易而且环境污染小、废水处理简单,可以取代传统化学沉铜工艺、投入规模生产。     

文献与摘要（104）

挠性印制板电镀铜的改善 当前挠性印制板（FPC）趋于越来越薄,要求可弯折性更高,应考虑更高的互连可靠性。文章针对高密度薄FPC的铜导体连接可靠性提出电镀铜的要求,及改善电镀铜层性能的新工艺。电镀铜层性能考虑有尺寸稳定性、热应力可靠性、与化学沉铜兼容性、镀层均匀性和表面平整性等,改变传统电镀铜工艺可达到新要求。     

行波管电镀铜螺旋线高温处理后变色问题的实验分析

对行波管螺旋线电镀铜工艺进行了描述和分析,从实验上阐明了烧氢后螺旋线表面颜色变化的原因。实验分析表明,Ni-Cu合金化反应是导致颜色变化的主要原因,而合金化的结果使表面电导率、热导率大大降低,因此,电镀铜工艺不适合于行波管螺旋线的表面处理。在此基础上,对螺旋线镀铜工艺的其他技术方案进行了评述。     

灭菌剂在PCB制造中的应用与研究

介绍了一种灭菌剂在PCB电镀制程中的应用情况,通过实验数据得出,其对改善因水质问题引起的板面铜渣、铜丝等不良现象有明显的效果,同时对改善生产线的水质和节省用水量也有一定的作用。它对PCBT的产品品质、成本节约和环保等方面均具有积极的意义,具有良好的推广价值。     

PCB电镀铜工艺和常见问题的处理

印制电路板（PCB）电镀主要包括电镀铜、电镀锡、电镀镍和电镀金等。其中电镀铜是PCB制作中的一个重要工艺,文章主要介绍电镀铜的工艺技术、应注意的操作技术问题和一些常见问题的处理方法。     

Fabrication of high aspect ratio copper nanowires using supercritical CO2 fluids electroplating technique in AAO template

This study utilizes the supercritical and post-supercritical electroplating technique, to fabricate copper nano-wires inside ultra-high aspect ratio Anodic Aluminum Oxide templates (AAO templates). Comparisons of the electroplating capabilities and results were made between these methods and the more common traditional electroplating techniques. Under identical experimental conditions and on ultra-high aspect ratio AAO template with thickness of 60 µm (aspect ratio of 1:490), it is evident from the results that the supercritical electroplating process has the fastest electroplating velocity of the three processes (~1.33 µm/min), followed by post-supercritical electroplating (~1 µm/min) and traditional electroplating is the slowest (~0.67 µm/min). This study also discusses the electroplating quality of the copper nano-wires. Samples were sliced along the cross-section, and Field Emission Scanning Electron Microscopy (FESEM) was utilized to observe the copper nano-wires. X-Ray Diffraction (XRD) was used to observe that the crystal structures is polycrystalline, and with the use of equations it is determined that grain size will not be severely affected by changes in current density and supercritical pressure in themselves, but instead the different processes do produce an evident change. The grain size achieved with supercritical electroplating is the smallest, followed by the post-supercritical electroplating, and the largest was given by the traditional electroplating process. Through these results it can be proved that supercritical electroplating process indeed provides grain refinement capabilities. The supercritical fluid-enabled electroplating process utilized for these experiments does not need addition of any surfactants to aid filling of the structures, but only relies on the intrinsic properties of supercritical fluids to achieve complete filling of nano-holes, and because there are no surfactants, we can achieve higher degree of purity in the copper nano-wires.     

High aspect ratio copper through-silicon-vias for 3D integration

Three-dimensional (3D) integration, which uses through-silicon-vias (TSVs) to interconnect multiple layers of active circuits, offers significant improvements over planar integrated circuits (ICs) on performance, functionality, and integration density. To address a key issue in 3D integration, the fabrication of high aspect ratio TSVs, this paper presents the bottom-up copper electroplating technique to fill high aspect ratio vias with copper. Deep through-silicon holes with aspect ratio as high as 10:1 are etched using deep reactive ion etching (DRIE) method, and are completely filled with copper using bottom-up copper electroplating technique without forming any voids or seams. Based on this technique, a multi-layer 3D integration method is proposed. This method uses temporary transfer wafer to provide mechanical support to the device wafer during wafer thinning process and to provide the seed layer for copper electroplating. Then bottom-up electroplating is performed to fill the high aspect ratio vias with copper. Experimental results verify the feasibility of the proposed method.     

The influence of ultrasonic agitation on copper electroplating of blind-vias for SOI three-dimensional integration

Three-dimensional (3D) integration, which employs through-silicon-vias (TSVs) to electrically interconnect multiple-stacked chips, is a promising technology for significant reduction in interconnect delay and for hetero-integration of different technologies. To fabricate void-free TSVs, this paper presents a copper electroplating technique with the assistance of ultrasonic agitation to fill blind-vias, and discusses the influence of ultrasonic agitation on copper electroplating. Blind-vias with an aspect ratio of 3:1 are used for copper electroplating with both direct current (DC) and pulse-reverse current modes, combined with either ultrasonic agitation or mechanical agitation. Experimental results show that blind-vias with small aspect ratio can be completely filled using pulse-reverse current, regardless of the agitation methods. For DC, ultrasonic agitation is superior to mechanical agitation for copper electroplating in filling void-free vias. These results indicate that agitation, though is a secondary control factor to pulse-reverse current, can enhance mass transfer in blind-vias during copper electroplating and can improve the filling capability of copper electroplating.     

活性氧化铜粉的工艺条件研究

研究开发了一条由纯铜片制备电镀级活性氧化铜粉的工艺方法。以铜片为原料,经过碳酸氢铵和氨水溶铜,常压脱氨,焙烧三阶段得到活性氧化铜粉。用SEM、ICP等方法对所得的活性氧化铜粉的性能进行了表征,结果表明,采用该法得到的活性氧化铜粉纯度达到99%以上,金属杂质含量和溶解速度完全符合电镀级氧化铜粉的要求,可以直接用到线路板的电镀工序。     

Void control during plating process and thermal annealing of through-mask electroplated copper interconnects

The quality of the sputtered copper film, which serves as the seed layer for sequent electroplating, becomes critical when the size of crack on the surface of the sputtered film is close to the feature size of the electroplated copper interconnect. The crack results in void formation in electroplated copper before thermal annealing and this phenomenon limits attainable highest anneal temperature. To solve this problem, the sputtered seed layer was slightly etched before electroplating process and a TaN passivation layer was deposited on the electroplated Cu interconnect before thermal annealing. Those processes not only suppressed void formation during the electroplating and annealing process at 300 °C, but also resulted in lower electrical resistance in the copper interconnects.     

密集散热区PTH孔问题研究

现有PCB局部散热技术主要是通过局部埋铜块或局部设计密集孔来实现散热。在电镀时由于密集孔区域与稀疏孔区域,存在明显的电位差,导致传统电镀方法及电镀线很难满足要求。文章主要通过设计不同的方法来验证并改善局部密集散热区域PTH镀铜品质问题。     

Dual damascene advanced interconnects: new copper seed layer enhancement process metrology using ion chromatography

Physical vapor deposition (PVD) copper seeding and subsequent fill by electroplating have become the most attractive technique for the implementation of copper metallization. However, a PVD seed layer provided as a continuous thin film with low resistivity to carry current for the subsequent electroplating process might have limitations of poor step coverage, rough morphology, discontinuity, overhang, and coverage asymmetry. Hence, it is of importance to extend the capability of PVD seed-layer deposition process for future high performance devices. An ion chromatography (IC) method is shown to be capable for electrochemical copper seed layer enhancement (SLE) process metrology. Composition dynamics of fresh and aged SLE bath solutions with an electroplating time up to 66.5 min are measured and analyzed with an IC system. The solution dynamics are found to be significant for electroplated copper film properties, the resistivity and roughness, which are found to be crucial for filling by electroplating the sub-0.2 μm vias and trenches of high aspect ratio. A strong correlation between the ion chromatograms and the electroplated copper film properties is observed.     

IC键合铜线材料的显微力学性能研究

用于IC(集成电路)的键合铜线材料具有低成本、优良的导电和导热性等优点,但其高硬度容易对铝垫和芯片造成损伤,因此对其硬度的测量是一项关键技术。纳米压痕测量技术可以方便、准确地测量铜线材料的显微硬度值和其他力学性能参数。描述了纳米压痕测量技术的原理以及对铜线材料样品进行纳米压痕测量的参数选择,进行了测量试验。结果表明,原始铜线、FAB(金属熔球)、焊点的平均硬度分别为1.46,1.51和1.65GPa,为键合铜线材料的选择和键合工艺参数的优化提供了依据。