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一、概述 随着亚微米工艺的日趋成熟,MOS集成电路的集成度也随之大幅度提高,所用的SiO_2在不断地减薄。例如,64KDRAM(动态随机存贮器)的氧化层厚度为30~40nm,256KDRAM的氧化层厚度为15~25nm,1MDRAM和电可擦可编程序唯读存贮器(EEPROM的氧化层厚度小于10nm。如图1所示。 氧化层不仅可用作MOSFET的栅介质,还可构成动态存贮器的存贮电容,并提供器件之间的隔离层。随着集成度的提高,芯片面积不断增大,器件尺寸按比例缩小,栅介质的不稳定和击穿等成为MOS集成电路失效的主要原因。例如,在EEPROM中,隧道击穿是导致其疲劳损坏的主要原因。因此,了解、分析、提高超薄栅介质的稳定性与可靠性是十分必要的。 相似文献
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重点讨论了在斜波脉冲条件下,EEPROM中fiotox管在浮栅充电放电过程中阈值电压的变化,对原有模型进行了补充,修正,所得结果与实验相符。 相似文献
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应用直接隧道比例差分(DTPDO)谱技术研究了深亚微米MOS器件超薄栅氧化层的应力诱生缺陷。实验结果发现超薄栅氧化层直接隧道栅电流的比例差分谱存在明显的三个谱峰。这意味着在超薄栅氧化层退化的过程中有三种氧化层高场诱生缺陷共存。研究结果表明,三种缺陷的饱和缺陷密度均随着应力电压和应力温度的增加而增加。三种缺陷的特征产生时间常数与器件的实验温度、所加的应力电压和氧化层的失效时间相关。 相似文献
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本文主要讨论超薄栅介质和隧道氧化层的各种击穿机理,以及评价参数,并结合实际探讨超薄栅介质和隧道氧化层的测试结构,测试和分析技术等有关击穿特性的论证方法,为亚微米工艺,E2PROM工艺和Flashmemory工艺的研究和开发提供一定的技术支撑。 相似文献
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介绍了在纳米晶浮栅存储器数据保持特性方面的研究工作,重点介绍了纳米晶材料的选择与制备和遂穿介质层工程。研究证明,金属纳米晶浮栅存储器比半导体纳米晶浮栅存储器具有更好的电荷保持特性。并且金属纳米晶制备方法简单,通过电子束蒸发热退火的方法就能够得到质量较好的金属纳米晶,密度约4×1011cm-2,纳米晶尺寸约6~7nm。实验证明,高介电常数隧穿介质能够明显改善浮栅存储器的电荷保持特性,所以在引入金属纳米晶和高介电常数遂穿介质之后,纳米晶浮栅存储器可能成为下一代非挥发性存储器的候选者。 相似文献
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对浮栅晶体管进行了60Co-γ射线总剂量辐照试验,研究了浮栅晶体管的电离辐射响应特性,通过对晶体管在辐照后的常温和高温100℃下的退火,分析了电离辐射环境下浮栅晶体管的陷阱电荷的产生及变化过程,监测了浮栅电荷存储能力。结果表明,辐照导致浮栅晶体管中多晶硅浮动栅极存储电荷的丢失,界面处感生的陷阱电荷数量远少于氧化物陷阱电荷及浮栅中电荷丢失量,退火效应可恢复浮栅受辐射影响的存储能力。试验数据为浮栅晶体管在电离辐射环境的测试及应用提供参考。 相似文献
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EEPROM单元辐射机理研究 总被引:1,自引:0,他引:1
随着EEPROM存储器件在太空和军事领域的广泛应用,国际上对EEPROM抗辐射性能的研究越来越多。为了满足太空及军事领域的需要,文章分别研究了FLOTOX和SONOS两种EEPROM工艺制成的存储单元在辐射条件下所受的影响,比较了FLOTOX和SONOS单元抗辐射性能的优劣,得出由于FLOTOX单元受工艺和结构的限制,抗辐射性能不如SONOS单元。同时在做抗辐射加固设计时,FLOTOX单元还需要考虑到电压耦合比的问题,且不利于等比例缩小。文章的研究不但满足了目前的工作需要,还为以后抗辐射EEPROM制作提供了理论基础。 相似文献
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Device simulation is used to investigate three-dimensional effects in small electrically erasable programmable read-only memory (EEPROM) cells. Threshold voltage, tunnel currents, write speed, and the effects of misregistration are characterized for a structurally parameterized generic FLOTOX EEPROM cell. The results indicate considerable sensitivity to three-dimensional effects. Design insights for small EEPROM cells are discussed 相似文献
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本文首先从理论上分析FLOTOX EEPROM隧道氧化层中陷阱俘获电荷对注入电场和存储管阈值电压的影响,然后给出了在不同擦写条件下FLOTOX EEPROM存储管的阈值电压与擦写周期关系的实验结果,接着分析了在反复擦写过程中陷阱俘获电荷的产生现象.对于低的擦写电压,擦除阈值减少,在隧道氧化层中产生了负的陷阱俘获电荷;对于高的擦写电压,擦除阈值增加,产生了正陷阱俘获电荷.这一结果与SiO2中电荷的俘获——解俘获动态模型相吻合. 相似文献
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EEPROM失效机理初探 总被引:3,自引:2,他引:1
在分析了双层多晶硅FLOTOXEEPROM各种失效模式后,从理论上提出了提高EEPROM可靠性的各种措施。提高隧道氧化层和多晶硅之间氧化层的质量,减小擦/写电压和擦/写时间,减小隧道氧化层的面积,都是提高EEPROM可靠性的有效措施。 相似文献
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随着EEPROM存储器件在太空和军事领域的广泛应用,国际上对EEPROM抗辐射性能的研究越来越多。为了达到提高存储器件抗辐射性能的目的,文章从版图设计的角度出发,首先分析了辐射对器件造成的影响,接下来分别介绍了基于FLOTOX和SONOS工艺的EEPROM器件特性,同时指出了在版图设计时需要注意的电压耦合比的问题。在设计中,利用管内隔离和管间隔离的方法,使得管内源/漏端和相邻两管源/漏端之间没有场氧介入,或是将场氧隔开,不让场区下形成漏电通道。设计出的EEPROM版图,不但满足了目前的工作需要,同时为以后抗辐射版图设计提供了有用的参考。 相似文献
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Papadas C. Pananakakis G. Ghibaudo G. Riva C. Pio F. Ghezzi P. 《Electron Devices, IEEE Transactions on》1995,42(4):678-682
A model for the intrinsic retention characteristics of FLOTOX EEPROM cells is presented, which is based on the temperature dependence of the Fowler-Nordheim emission current. This model which has been successfully tested on single-poly-FLOTOX EEPROM cells, enables the device lifetime to be calculated for given memory operating conditions, instead of being extrapolated as is usually done. The sensitivity of the retention characteristics to several technological parameters is also investigated. It is expected that this intrinsic retention model (with minor modifications) will also be applicable to FLASH EEPROM cells 相似文献
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Papadas C. Ghibaudo G. Pananakakis G. Riva C. Ghezzi P. 《Electron Device Letters, IEEE》1992,13(2):89-91
A theoretical model that explains the programming window degradation and the corresponding high- and low-state threshold voltage shifts as a function of the number of write-erase operations in FLOTOX EEPROM cells is proposed. The collapse of the programming window is quantitatively related to the oxide charge buildup in the FLOTOX tunnel region as the cycling of the memory cell is increased. The simplicity of the model should make possible a direct application at CAD level 相似文献
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A model for the simulation of the programming operations of a FLOTOX EEPROM cell is proposed. The model takes into account the following phenomena occurring during the erase operation: (1) depletion layers in the tunnel (thin) oxide area, the channel area, the poly-drain overlap area and the source diffusion area; (2) band to band tunnelling in the tunnel area; (3) impact ionization of the tunnelling electrons; and (4) channel depletion. Results for the write operation are also presented as a comparison. The computer model serves as a tool for theoretical understanding of the programming operation of the FLOTOX EEPROM, and a model for future CAD tools. Results of the simulation show the appearance of an anomalous tunnel current peak that compares well with the experimental results presented by other authors. 相似文献
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Yamauchi Y. Tanaka K. Sakiyama K. Miyake R. 《Electron Devices, IEEE Transactions on》1992,39(12):2791-2796
A versatile stacked storage capacitor on FLOTOX (SCF) structure is proposed for a megabit nonvolatile DRAM (NV-DRAM) cell that has all the features required for NVRAMs. The SCF structure realizes a 30.94-μm 2 NV-DRAM cell with 0.8-μm design rules and allows an innovative flash store/recall (DRAM to EEPROM/EEPROM to DRAM) operation that does not disturb original data in DRAM or EEPROM. This store operation is completed in less than 10 ms. The single cell shows excellent reliability such as store endurance greater than 106 cycles and EEPROM data retention in excess of 10 years under high storage temperatures of 150°C and DRAM write operation at 85°C. The SCF cell has been successfully implemented into the 1 Mb NVRAM 相似文献