MIM与MIS隧道发光结发光机制的讨论

ＭＩＭ（Ｍｅｔａｌ－Ｉｎｓｕｌａｔｏｒ－Ｍｅｔａｌ）与ＭＩＳ（Ｍｅｔａｌ－Ｉｎｓｕｌａｔｏｒ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）隧道发光结为新型全固态薄膜发光器件,在对基本结构简单介绍后,结合发光光谱,着重对ＭＩＭ与ＭＩＳ结发光所涉及的几种发光机制进行了分析讨论。     

微晶纤维素超显微结构的扫描隧道显微镜研究

本文以微晶纤维素Ｓｉｇｍａｃｅｌｔｙｐｅ５０为材料，用扫描隧道显微镜（ＳＴＭ）对其结构进行了研究，结果表明用ＳＴＭ可以直接观察到纤维素的基原纤丝（ｅｌｅｍｅｎｔａｒｙｆｉｂｒｉｌ），其直径为２—３纳米。从表面观察，微晶纤维素的基原纤丝平行排列在一起，其本身呈螺旋状，基原纤丝进一步聚合在一起，形成微纤丝（ｍｉｃｒｏｆｉｂｒｉｌ）。从横切面也观察到了基原纤丝的大小和排列。从纳米水平直接观察到基原纤丝的结构尚属首次，ＳＴＭ是观察纤维素超显微结构的有效工具。     

微晶纤维素超微结构的扫描隧道显微镜研究

本文以微晶纤维素Ｓｉｍｇａ ｃｅｌｌ５０为材料，用扫描隧道显微镜（ＳＴＭ）对其结构进行了研究，结果表明用ＳＴＭ可以直接观察到纤维素的基原纤丝（ｅｌｅｍｅｎｔａｒｙ ｆｉｂｒｉｌ），其直径为２－３纳米。从表面观察，微晶纤维素的基原纤丝平行排列在一起，其本身呈螺旋状，基原纤丝进一步聚合在一起，形成微纤丝（ｍｉｃｒｏｆｉｂｒｉｌ）。从横切面也观察到了基原纤丝的大小和排列。从纳米水平直接观察到基原纤丝的结     

高场应力下FLOTOXMOS管的性能退化研究

利用氧化层动态电流弛豫谱分析方法,测试分析了在周期性电场应力下ＦＬＯＴＯＸＭＯＳ管隧道氧化层中陷阱电荷的特性,为研究陷阱电荷对ＦＬＯＴＯＸ ＥＥＰＲＯＭ 阈值电压的影响提供了实验依据。在＋ １１ Ｖ、－ １１ Ｖ 周期性老化电压下所产生的氧化层陷阱电荷饱和密度分别为－ １．８×１０１１ ｃｍ － ２和－ １．４×１０１１ ｃｍ － ２,平均俘获截面分别为５．８×１０－ ２０ ｃｍ ２ 和７．２×１０－ ２０ ｃｍ ２,有效电荷中心距分别为３．８ ｎｍ 和４．３ ｎｍ ,界面陷阱电荷饱和密度分别为６．５４×１０９ ｃｍ － ２ｅＶ－ １和－ ３．８×１０９ ｃｍ － ２ｅＶ－ １,平均俘获截面分别为１．１２×１０－ １９ ｃｍ ２ 和４．９×１０－ １９ ｃｍ ２。     

DEM技术中微复制工艺研究

利用ＤＥＭ（Ｄｅｅｐｅｔｃｈｉｎｇ，Ｅｌｅｃｔｒｏｆｏｒｍｉｎｇ，Ｍｉｃｒｏｒｅｐｌｉｃａｔｉｏｎ）技术获得的微复制金属模具进行了微复制工艺研究。对微复制工艺参数进行了优化，在ＰＣ、ＰＭＭＡ和ＰＯＭ塑料上获得了高深宽比的微结构，并对ＰＣ、ＰＭＭＡ和ＰＯＭ和不同图形的微复制效果进行了比较。     

MICROTUNE推出CABLE宽带应用RF上行信号放大器

世界著名的ＭｉｃｒｏｔｕｎｅＴＭ 公司日前宣布推出业界性能最高且功耗最低的新型ＲＦ上行信号放大器ＭｉｃｒｏＳｔｒｅａｍｅｒＴＭ ,以供宽带ｃａｂｌｅｍｏｄｅｍ、ｃａｂｌｅ电话、机顶盒和数字交互式领域的应用。Ｍｉｃｒｏｔｕｎｅ的这种用于交互式消费类电子设备的全芯片双向ＲＦ“通路”产品丰富了Ｍｉｃｒｏｔｕｎｅ的芯片种类 ,而且处理性能、速度和可靠性更高。此新型射频（ＲＦ）上行信号放大器系列中的第一个产品单芯片部件为ＭＴ１５３０ ,该Ｍｉｃｒｏ -ＳｔｒｅａｍｅｒＭＴ１５３０支持ＤＯＣ ＳＩＳ和ＥｕｒｏＤＯＣＳ…     

McAfee Office2000 Pro优化PC性能保障网络安全

ＮＡＩ公司的ＭｃＡｆｅｅ软件部开始发行ＭｃＡｆｅｅＯｆｆｉｃｅ２０００Ｐｒｏ。这是一个先进的综合性软件包,它为用户提供所需要的一切工具,用以对他们的ＰＣ进行加固、保护、修理和优化。ＭｃＡｆｅｅＯｆｆｉｃｅ２０００Ｐｒｏ将把ＭｃＡｆｅｅＯｆｆｉｃｅ２０００中已引入的用户界面加以扩展,提供一种前所未有的高水平的向导,很容易帮助用户找到该软件包中的各种工具。它既包含了ＭｃＡｆｅｅＯｆｆｉｃｅ２０００的所有模块,如ＶｉｒｕｓＳｃａｎ、ＭｃＡｆｅｅＵｔｉｌｉｔｉｅｓ、ＦｉｒｓｔＡｉｄ、Ｕｎｉｎｓｔｔａｌ…     

热成像温差分辨率与微分光谱匹配因数的关系

由近距离低温面目标热成像系统的信号方程和噪声等效温差ＮＥＴＤ的定义，导出了ＮＥＴＤｏｃ１／Ｍ，并由此得到ＭＲＴＤｏｃ１／Ｍ，ＭＤＴＤｏｃ１／Ｍ，从而证明了热成像系统的温差分辨率；ＮＥＴＤ、ＭＲＴＤ、ＭＤＴＤ均要求微发光谱匹配因数Ｍ要大，这为选用光谱区配因数Ｍ和Ｍ作为热成像系统的综合评价参数奠定了理论基础。     

Microchip科技推出8管脚闪存和PIC18结构

Ｍｉｃｒｏｃｈｉｐ科技推出两款 8管脚闪存单片机ＰＩＣ18Ｆ0 10和ＰＩＣ18Ｆ0 2 0 ,进一步扩充了Ｍｉｃｒｏｃｈｉｐ的闪存系列和功能强大的ＰＩＣ18结构器件。两款芯片都采用Ｍｉｃｒｏｃｈｉｐ最新的 0 .5μｍ工艺 ,在一个小型 8管脚封装内具备了 10ＭＩＰＳ的业界领先性能、4 8Ｋ程序存储器、2 56字节ＲＡＭ ,以及64字节ＥＥＰＲＯＭ数据存储器。在扩充现有的ＰＣ主板功能时 ,管脚兼容性减少了样机研究时间 ,可节省成本。因为软件可跨平台重复使用 ,两种器件跨 8到 84管脚ＰＩＣｍｉｃｒｏ结构的编码兼容性 ,又可节省开发时间和成本。…     

多芯片组件──封装技术的现状与未来

多芯片组件──封装技术的现状与未来ＭｕｌｔｉｃｈｉｐＭｏｄｕｌｅｓ：ＴｈｅＰａｃｋａｇｉｎｇＴｅｃｈｎｏｌｏｇｙｏｆＴｏｄａｙ···ａｎｄＴｏｍｏｒｒｏｗＴｉｍｏｔｈｙＬ．Ｈｏｄｓｏｎ等１ＭＣＭ为电子材料和电子设备展示光明前景，工业界人士分析了ＭＣＭ...     

纳米吸波材料的物理实质及研究进展

吸波材料是隐身技术的关键材料,纳米材料由于其特殊的量子尺寸效应和隧道效应等产生的优良的电磁波吸收性能而受到世界各国的重视．本文简单介绍了吸波材料的工作原理,进而阐述了纳米吸波材料吸收电磁波的物理实质．详细介绍了纳米涂敷型吸波材料和纳米结构型吸波材料的研究现状,并对纳米吸波材料的发展趋势进行了展望．     

STM·IPC-205B型扫描隧道显微镜的技术与应用

扫描隧道显微镜(STM)作为纳米科技中最为有效和重要的检测加工手段之一,其应用随着纳米科技热的兴起而日益引起人们的重视。本文简述了STM·IPC-205B型机的工作原理及应用,以具体实例的STM扫描图像说明STM具有广阔的应用前景。     

应用CO2激光器制备STM光纤探针的研究

以普通的单模石英光纤为材料,改进熔融拉锥装置,利用有旋转曲面的凹面镜,实现了制作扫描隧道显微镜光纤探针的加工过程.实验表明,改进后的拉锥装置满足了制作纳米量级针尖曲率半径光纤探针的基本要求.     

Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO

Design optimization for performance enhancement in analog and mixed-signal circuits is an active area of research as technology scaling is moving towards the nanometer scale. This paper presents an approach towards the efficient simulation and characterization of mixed-signal circuits, using a 45 nm CMOS voltage controlled oscillator (VCO) with frequency divider as a case study. The performance characteristics of the analog and digital blocks in the circuit are simulated and the accuracy issues arising due to separate analog and digital simulation engines are considered. The tremendous impact of gate tunneling current on device performance is quantitatively analyzed with the help of an “effective tunneling capacitance”, which allows accurate modeling and simulation of digital blocks with almost analog accuracy. To meet the design specifications of the analog VCO using digital CMOS technology, we follow a design of experiments (DOE) approach. The functional specifications of the VCO optimized in this design are the center frequency and minimization of overall power consumption as well as minimization of power due to gate-oxide tunneling current leakage, a component that was not important in previous generations of CMOS technologies but is dominant at 45 nm and below. Due to the large number of available design parameter (gate-oxide thickness and transistor sizes), the concurrent achievement of all optimization goals is difficult. A DOE approach is shown to be very effective and a viable alternative to standard design exploration in the nanometer regime.     

Role of structure sizes in determining the characteristics of the resonant tunneling diode

Using the Wigner function formalism, we study the effects of structural parameters on the DC I-V characteristics and on the large-signal transient response of the resonant tunneling diode. We model two types of structures of GaAs/Al_xGa_1-xAs; first, with symmetric barriers ranging from 3 to 8 nanometers in thickness separated by a 5 nanometer well, and second with a well varying from 3 to 8 nanometers between 3 nanometer barriers. Experimental variation of the barrier thickness and height changes the peak-to-valley ratio in the I-V curve, as predicted by elementary models of tunneling structures. This stems directly from the changes in tunneling probabilities. For the DC studies, we show that the peak-to-valley ratio in the I-V curve is a function of the resonance width, which depends both on the well and barrier thickness. The location of the peak on the I-V curve depends on the location of the resonant energy, which is a function of the well width. Transient switching behavior is compared to earlier numerical studies of tunneling times of wave packets. Charge storage stabilizes the position of the resonant state, thus damping the transients. Consequently, wider barriers yield faster transient settling times, in agreement with the tunneling time results which predicted longer charge storage times for thicker barriers.     

直接隧穿栅电流对CMOS逻辑电路的影响

对于纳米级的CMOS电路,由于MOS器件具有超薄的氧化层,栅隧穿漏电流的存在严重地影响了电路的正常工作。本文基于可靠性理论和电路级仿真深入地研究直接隧穿电流对CMOS逻辑电路的影响。仿真结果很好地与理论分析相符合,这些理论和仿真将有助于以后的集成电路设计。     

部分耗尽型绝缘体上硅器件体接触结构及新的方法对于对抑制浮体效应的研究

随着SOI CMOS工艺不断缩微,最小栅宽进入几十纳米时,用浮体接触结构抑制浮体效应就越来越无效,这是由于顶层硅的不断减薄带来越来越高的浮体串联电阻,使得堆积在浮体内的载流子越来越难流出体外。文章详细分析了传统体接触结构不能有效抑制浮体效应的原因,并且介绍了新的SOI CMOS结构用来抑制SOI的浮体效应。     

Body-contact self-bias effect in partially depleted SOI-CMOS and alternatives to suppress floating body effect

As SOI-CMOS technology nodes reach the tens of nanometer regime,body-contacts become more and more ineffective to suppress the floating body effect.In this paper,self-bias effect as the cause for this failure is analyzed and discussed in depth with respect to different structures and conditions.Other alternative approaches to suppressing the floating body effect are also introduced and discussed.     

Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits

Leakage currents are gaining importance as design parameters in nanometer CMOS technologies. A novel leakage current estimation method, which takes into account the dependency of leakage mechanisms, is proposed for general CMOS complex gates, including non-series-parallel transistor arrangements, not covered by existing approaches. The main contribution of this work is a fast, accurate, and systematic procedure to determine the potentials at transistor network nodes for calculating standby static currents. The proposed method has been validated through electrical simulations, showing an error smaller than 7% and an 80× speed-up when comparing to electrical simulation.     

纳米CeO_2的制备方法及应用研究进展

综述了纳米CeO2的几种主要制备方法及其研究进展,并介绍了纳米CeO2的主要应用领域和研究前沿。