应用于PHEMT器件的深亚微米T形栅光刻技术

PHEMT器件和基于它的高频单片集成电路广泛应用于现代微波/毫米波系统。当PHEMT器件的栅长缩短到足够短的时候,沿着栅宽方向的寄生电阻会影响PHEMT器件的性能。为了解决这个问题,一种具有大截面面积而底部长度却很小的T形栅结构通常被用于制作PHEMT器件,因为这种结构可以有效地减少由于栅寄生电阻而引起的晶体管噪声。对几种常用的制作深亚微米T形栅的三种光刻技术即光学光刻、电子束光刻、X射线光刻技术进行了比较分析。对于光学光刻技术,通常需要采用移相和光学邻近效应校正技术,它的制作成本低,但是很难用于制作深亚微米T形栅;对于电子束光刻技术,通常需要采用高灵敏度和低灵敏度的多层胶技术,虽然它的栅长可以制作到非常小,但是它的生产成本非常高,而且它的生产效率非常低;对于X射线光刻技术,它不仅可以用于制作深亚微米T形栅,而且它的生产效率非常高,T形栅的形状可以非常容易控制。     

深亚微米同步辐射x射线光刻技术

报道了我们制作深亚微米 x射线掩模的工艺和同步辐射 x射线曝光工艺 ,并报道了我们在北京同步辐射装置 (BSRF) 3B1 A光刻束线所获得的深亚微米 x射线光刻图形的实验结果     

深亚微米同步辐射x射线光刻模拟

用束衍生法研究了深亚微米同步辐射x射线光刻中掩模吸收体的光导波效应,并对x射线光刻后的光刻胶剖面进行了理论计算。采用面向对象技术,研制了一个取名为XLLS1.0的模拟软件。本文对这个软件进行了详细介绍。     

深亚微米同步辐射x射线光刻技术

报道了我们制作深亚微米ｘ射线掩模的工艺和同步辐射ｘ射线曝光工艺，并报道了我们在北京同步辐射装置（ＢＳＲＦ）３Ｂ１Ａ光刻束线所获得的深亚微米ｘ射线光刻图形的实验结果。     

采用移相掩模技术制作深亚微米“T”型栅

介绍了在GaAs器件制作中,如何提高光刻细线条加工能力、制作深亚微米"T"型栅的工艺技术。该技术采用投影光刻和负性化学放大光刻胶,制作出0.18μm的"T"型栅GaAs PHEMT器件,栅光刻工艺采用了分辨率增强移相掩模技术。根据曝光工具简单介绍了当前GaAs器件中"T"型栅主要制作方法,讨论了"T"型栅制作中所使用的移相掩模原理以及该技术应用于GaAs器件制作的优势,并介绍了工艺制作过程。给出了所制作的"T"型栅扫描电镜剖面照片,并进一步试验、讨论和分析了采用该种移相掩模版进行光刻时所遇到的主要困难及解决方向。     

深亚微米同步辐射x射线光刻模拟

用束衍生法研究了深亚微米同步辐射 x射线光刻中掩模吸收体的光导波效应 ,并对 x射线光刻后的光刻胶剖面进行了理论计算。采用面向对象技术 ,研制了一个取名为 XLLS1 .0的模拟软件。本文对这个软件进行了详细介绍     

高温恒定电场栅氧化层TDDB寿命测试方法研究

介绍了薄栅氧化层TDDB可靠性评价的高温恒定电场试验方法,并完成了E模型的参数提取,同时以MOS电容栅电流Ig为失效判据。对某工艺的MOS电容栅氧化层TDDB寿命进行了评价。该试验方法解决了在高温条件下对工作器件进行可靠性评价的问题,方法简便可靠,适用于亚微米和深亚微米工艺线的可靠性评价。     

亚微米/深亚微米的栅氧清洗技术

栅氧前清洗是栅氧工艺的重要部分,本文介绍二种适用于亚微米/深亚微米的清洗工艺: 采用稀释化学试剂和兆声波清洗的VCS清洗工艺和IMEC清洗工艺。     

FPGA的静态功耗分析与降低技术

FPGA已经被广泛用于实现大规模的数字电路和系统,随着CMOS工艺发展到深亚微米,芯片的静态功耗已成为关键挑战之一。文章首先对FPGA的结构和静态功耗在FPGA中的分布进行了介绍。接下来提出了晶体管的漏电流模型,并且重点对FPGA中漏电流单元亚阈值漏电流和栅漏电流进行了详细的分析。最后根据FPGA的特点采用双阈值电压晶体管,关键路径上的晶体管采用低阈值电压栅的晶体管,非关键路径上的晶体管采用高阈值电压栅的晶体管,以此来降低芯片的静态功耗。     

基于IEP的高密度等离子体刻蚀过程终点检测技术

高密度等离子体刻蚀是当今超大规模集成电路制造过程中的关键步骤.随着集成电路中器件尺寸的缩小及器件集成密度的提高,对刻蚀过程终点的准确判断是目前所面临的一个严峻考验,传统的OES终点检测技术已经远远不能满足深亚微米刻蚀工艺需求.讨论IEP终点检测技术的原理,针对多晶硅栅的等离子体刻蚀工艺,讨论了IEP终点检测技术在深亚微米刻蚀工艺中的应用,IEP预报式终点检测技术已经运用在新近研发的HDP刻蚀机的试验工艺上,最后对IEP终点检测技术未来的发展趋势进行了展望.     

Submicron T-shaped gate HEMT fabrication using deep-UV lithography

A new combination of low/high/low sensitivity tri-layer (PMMA/PMIPK/PMMA) resist system was used for deep UV lithography to-fabricate submicron T-shaped gate. Gate length as narrow as 0.2 μm is achieved. GaAs HEMTs with 0.3 μm T-shaped Ti/Pt/Au gate are fabricated using this technology. The HEMT demonstrated a 0.6 dB noise figure and 13 dB associated gain at 10 GHz. This deep UV lithography process provides a high throughput and low cost alternative to E-beam lithography for submicron T-gate fabrication     

用于T形栅光刻的新型移相掩模技术

根据移相掩模基本原理,通过光刻工艺模拟提出了一种适于T形栅光刻的新型移相掩模技术——M-PEL。初步实验证明,M-PEL技术可在单层厚胶上经一次光刻形成理想的T形栅抗蚀剂形貌。     

Four-layer resist process for asymmetric gate recess

In this paper, we present an optimized four-layer resist (PMMA and its copolymers) process for the fabrication of T-shaped gates used in compound semiconductor field effect transistors (FETs). The process is capable of producing a profile which acts as both the etch mask for the wide, asymmetric recess trench as well as the liftoff mask for a T-shaped gate metal. The resist profile is achieved in a single step using electron beam lithography, eliminating the need for two separate lithography steps and the crucial alignment between them. Gate lengths of 100 nm are achieved using this process. Recess widths on the drain side of the gate range from 50 to 300 nm, and recess widths on the source side of the gate are 50 nm.     

Evolution of T-shaped gate lithography for compound semiconductors field-effect transistors

T-shaped gate formation is a major processing step in the fabrication of high-performance FET-based III-V devices. Traditional bilayer or trilayer E-beam lithography methods using PMMA/(PMMA&PMAA) copolymers are high-cost options which also lack the required critical dimension control for manufacturing. Lithography methods that use only a single layer of PMMA for the formation of T-shaped gate stem, and routine I-line resist lithography for the tee-top, i.e., hybrid T-shaped gates, have been developed and extensively used in manufacturing. This approach has also been extended to the fabrication of deep submicron T-shaped gates using all I-line optical lithography. Both chemical shrinks and chromeless phase-shift resolution enhancement techniques have been investigated.     

Analysis of issues in gate recess etching in the InAlAs/InGaAs HEMT manufacturing process

We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13 μm–0.16 μm to suit the intended application. The core processes are a two-step electron-beam lithography process using a three-layer resist and gate recess etching process using citric acid. An electron-beam lithography process was developed to fabricate a T-shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three-layered resist and two-step electron beam exposure and development. Citric acid-based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.     

0.1μm T型栅PHEMT器件

通过电子束和接触式曝光相结合的混合曝光方法,并利用复合胶结构,一次电子束曝光制作出具有T型栅的PHEMT器件,并对0.1μm栅长PHEMT器件的整套工艺及器件性能进行了研究．形成了一整套具有新特点的PHEMT器件制作工艺,获得了良好的器件性能(ft=93.97GHz;gm=690mS/mm)．     

Ultra low noise characteristics of AlGaAs/InGaAs/GaAs pseudomorphicHEMT's with wide head T-shaped gate

The fully passivated low noise AlGaAs/InGaAs/GaAs pseudomorphic (PM) HEMT with 0.13 μm T-shaped gate was fabricated using dose split electron beam lithography method (DSM). This device exhibited low noise figures of 0.31 and 0.45 dB at 12 and 18 GHz, respectively. These noise figures are the lowest value ever reported for the GaAs based HEMT's. These results are attributed to the extremely low gate resistance which results from wide head T-shaped gate having the higher ratio more than 10 of gate head length to gate footprint     

0.15 μm T-shaped gate fabrication for GaAs MODFET using phaseshift lithography

A new fabrication process of GaAs MODFETs with 0.15 micron T-shaped gate has been developed by using phase shift lithography. Sub-quarter micron footprints of T-shaped gates are defined as line patterns by PEL (pattern-edge line) method using chemically stable positive photoresist. Parasitic capacitances such as C_gs and C_gd are also reduced by the air-gap incorporated in the present process. An implemented GaAs MODFET exhibited the NF of 0.36 dB and the gain of 11.5 dB at the frequency of 12 GHz     

Electron-beam fabrication of GaAs low-noise MESFET's using a new trilayer resist technique

A LO/HI/LO resist system has been developed to produce sub-half-micrometer T-shaped cross section metal lines using e-beam lithography. The system provides T-shaped resist cavities with undercut profiles. T-shaped metal lines as narrow as 0.15 µm have been produced. GaAs MESFET's with 0.25-µm T-shaped Ti/Pt/Au gates have also been fabricated on MBE wafers using this resist technique. Measured end-to, end 0.25-µm gate resistance was 80 ω/mm, dc transconductance gmas high as 300 mS/mm was observed. At 18 GHz, a noise figure as low as 1.4 dB with an associated gain of 7.9 dB has also been measured. This is the lowest noise figure ever reported for conventional GaAs MESFET's at this frequency. These superior results are mainly attributed to the high-quality MBE material and the advanced T-gate fabrication technique employing e-beam lithography.