一种基于总线复用的SoC功能测试结构设计

由于SoC结构的复杂性,必须考虑采用多种可测性设计策略.从功能测试的角度出发,提出了一种基于复用片内系统总线的可测性设计策略,使得片内的各块电路都可被并行测试.阐述了其硬件实现及应用测试函数编写功能测试矢量的具体流程.该结构硬件开销小,测试控制过程简单,可减小测试矢量规模,已应用到一种基于X8051核的智能测控SoC,该SoC采用0.35μm工艺进行了实现,面积为4.1 mm×4.1 mm,测试电路的面积仅占总面积的2%.     

系统芯片的可测性设计与测试

阐述了系统芯片(SoC)测试相比传统IC测试的困难,SoC可测性设计与测试结构模型,包括测试存取配置、芯核外测试层,以及测试激励源与测试响应汇聚及其配置特性、实现方法与学术研究进展,介绍了基于可复用内嵌芯核的SoC国际测试标准IEEE P1500的相关规约;最后,建议了在SoC可测性设计及测试中需要密切关注的几个理论问题。     

基于并行机制的边界扫描技术

在SoC测试时,测试功耗和测试成本是其可测性设计中最重要的一点要求.在分析了常见测试结构的测试功耗的基础上,提出了一种并行扫描机制的测试结构,包括访问机制的设计和测试控制器的设计.该方法可根据测试成本和测试功耗的要求,选择不同的构造方法.     

基于数字电视基带SoC芯片的可测性设计

介绍了基于数字电视基带SoC芯片的可测性设计方案.根据系统中不同模块的特点采取有针对性的可测性设计方案,对片内存储器进行内建自测试;对组合逻辑电路、时序逻辑电路采用近全扫描的测试方案;最后采用IEEE1149.1的控制单元作为芯片可测性设计部分的控制单元,控制芯片的测试功能.经测试,该可测性设计满足设计规划的面积和功耗的要求,并且系统的测试覆盖率达到了99.26%.     

一种SoC片上调试与可测性的整合设计

随着SoC的复杂度和规模的不断增长,SoC的片上调试与可测性变得越来越困难和重要。片上调试与可测性都是系统芯片设计的重要组成部分。文章针对某款32位SoC,充分利用CPU核原有的调试结构,提出一种可测试系统与调试系统的一体化结构设计,并针对不同的模块利用不同的测试策略。基于JTAG端口,该结构能够进行系统程序的调试、边界扫描的测试、扫描链的测试、嵌入式SRAM的内建自测试,同时有效地降低了电路逻辑规模,实现了在测试覆盖率和测试代价之间的一个有效折衷。     

SoC可测性设计中的几个问题

介绍了SoC可测性设计中的几个重要问题。包括在一般功能模块的扫描可测性设计中,如何实现对时钟、复位端、双向端口、芯片内部三态总线的控制,如何处理组合反馈环、锁存器、不同时钟沿触发的触发器、影子逻辑;以及在片上存储器内建自测试设计中,如何选择自测试的结构和算法。并结合一款基于ARM的SoC给出了实际可测性设计中具体的解决方法。     

Galileo/GPS双模相关器IP核设计

导航定位接收机中的相关器设计是导航定位接收机设计的一个关键技术,而相关器的设计将发展为基于SoC应用的IP核的设计。阐述了导航定位相关器的工作原理和结构,对构成相关器的各个模块进行了分析,并对Galileo/GPS的导航信号进行分析。在此基础上,采用基于SoC应用的IP核设计方法对Galileo/GPS双模相关器IP核进行设计,并进行了仿真验证和分析,可方便地应用于导航定位接收基带SoC的设计中。     

一种适合于SOC系统的JTAG扩展化可测性设计

随着集成电路系统复杂性的提高及基于 IP核的 SOC系统的出现 ,电路测试的难度不断增大 ,对电路可测性设计提出了更高的要求。文中在研究了现有各种可测性设计方法优劣后提出了扩展化的 JTAG可测性设计电路 ,它在稍增加电路复杂度的情况下融合各测试方法 ,并提出了利用这种测试电路的 IC系统测试方案。它克服了测试基于 IP核的 SOC系统的一些难点。     

SOC中IP核重用技术及其接口模型

SoC是超大规模集成电路的发展趋势和新世纪集成电路的主流.其复杂性以及快速完成设计、降低成本等要求,决定了系统级芯片的设计必须采用IP(Intellectual Property)重用的方法.本文介绍可重用IP设计方法,以及IP的接口模型,有效的接口可以提高重用率,从而提高SoC的设计效率.0CP(开放核协议)将软件中的分层概念应用到IP核接口,提供一种具有通用结构的接口协议,方便了IP核与系统的集成.     

一种基于嵌入式微处理器内核模块的测试

基于可复用的嵌入式IP内核模块的系统级芯片（SoC）设计方法使测试面临新的挑战。文章针对IP内核模块测试断面临的技术难点，介绍了IP核模块实现测试所需要构建的硬件环境和通用结构．并以嵌入ARM微处理器棱的SoC为例，提出了具体的测试解决方案。     

Wafer-Level Modular Testing of Core-Based SoCs

Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of core-based system-on-chip (SoC) designs. Packaging has been recognized as a significant contributor to the product cost for such SoCs. To reduce packaging cost and the test cost for packaged chips, wafer-level testing (wafer sort) is used in the semiconductor industry to screen defective dies. However, since test time is a major practical constraint for wafer sort, even more so than for package test, not all the scan-based digital tests can be applied to the die under test. We present an optimal test-length selection technique for wafer-level testing of core-based SoCs. This technique, which is based on a combination of statistical yield modeling and integer linear programming, allows us to determine the number of patterns to use for each embedded core during wafer sort such that the probability of screening defective dies is maximized for a given upper limit on the SoC test time. We also present a heuristic method to handle large next-generation SoC designs. Simulation results are presented for five of the ITC'02 SoC Test benchmarks, and the optimal test-length selection approach is compared with the heuristic method.     

Test Scheduling of NoC‐Based SoCs Using Multiple Test Clocks

Network‐on‐chip (NoC) is an emerging design paradigm intended to cope with future systems‐on‐chips (SoCs) containing numerous built‐in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC‐based SoCs. Among the existing test issues for NoC‐based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC‐based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC‐based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC’02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC‐based SoCs.     

MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip

The rapid migration to nanometer design processes has brought an unprecedented level of integration by allowing system designers to pack a wide variety of functionalities on-chip, namely, systems-on-a-chip (SoCs). In the meantime, electronic testing becomes an enabling technology for this SoC paradigm, since the integration of various core tests is a big challenge, and has revealed a widening gap between design and manufacturing. In particular, the increasing complexity and density of nanometer SoCs have led to the problem of visibility and accessibility in testing. In this paper, we propose an integrated wireless test framework to resolve the acerbated core accessibility problem and to eliminate the incompatibility between the existing SoC test strategies and the next generation billion-transistor SoC specification. Under such a test strategy, the intra-chip wireless links form the wireless test access mechanism (TAM) to transport test data chip-wide. We present a self-configurable multi-hop wireless test micronetwork, dubbed MTNet, with simple and efficient data transmission protocols, and develop a system level design-for-testability structure. Consequently, we propose a geographic routing algorithm to find the test access paths for the deeply embedded cores and a path driven test scheduling algorithm to design and integrate the MTNet-based SoC test access architecture. Extensive simulation study show the feasibility and applicability of MTNet.     

Low-Area Wrapper Cell Design for Hierarchical SoC Testing

System-on-chip (SoC) integrated circuits are designed and fabricated with multiple levels of hierarchy. However, most previous works on wrapper design, test access mechanism optimization and test scheduling did not take care of the hierarchy properly, thus the corresponding test schedules were often invalid for SoCs with hierarchical cores. We propose a low-area wrapper cell design which can treat SoCs with hierarchy properly and allows simultaneous testing of parent and child cores. The proposed cell uses 13%∼23% less area than a recently proposed cell design in equivalent gate count. As a result we achieve up to 21% area reduction for hierarchical ITC ’02 SoCs compared to the most recently proposed designs.     

FFI4SoC: a Fine-Grained Fault Injection Framework for Assessing Reliability against Soft Error in SoC

Recently, system-on-chips (SoCs) are increasingly employed in reliable applications for their high-performance and high-densities. Moreover, the structure shrinking of SoC leads to its proneness to radiation-induced soft errors. This paper presents a fine-grained fault injection framework for SoC (FFI4SoC) to assess the reliability of SoC against soft errors. FFI4SoC facilitates fault injection for SoC by defining the primary components and rules that are required by fine-grained fault injection. Furthermore, based on FFI4SoC, we develop a fine-grained fault injection tool named SSIFFI for bare-metal MicroZed. The design of SSIFFI is presented in order to illustrate the application of FFI4SoC. Finally, SSIFFI is engaged in simulated fault injection experiments to explore the cause of single event functional interrupts (SEFIs) and to validate functional properties of FFI4SoC. The experimental results disclose detailed reasons for SEFI and prove that FFI4SoC can be employed to assess reliability of SoC well with the merit of fine-grained injection.     

Process-Variation and Temperature Aware SoC Test Scheduling Technique

High temperature and process variation are undesirable phenomena affecting modern Systems-on-Chip (SoC). High temperature is a well-known issue, in particular during test, and should be taken care of in the test process. Modern SoCs are affected by large process variation and therefore experience large and time-variant temperature deviations. A traditional test schedule which ignores these deviations will be suboptimal in terms of speed or thermal-safety. This paper presents an adaptive test scheduling method which acts in response to the temperature deviations in order to improve the test speed and thermal safety. The method consists of an offline phase and an online phase. In the offline phase a schedule tree is constructed and in the online phase the appropriate path in the schedule tree is traversed based on temperature sensor readings. The proposed technique is designed to keep the online phase very simple by shifting the complexity into the offline phase. In order to efficiently produce high-quality schedules, an optimization heuristic which utilizes a dedicated thermal simulation is developed. Experiments are performed on a number of SoCs including the ITC’02 benchmarks and the experimental results demonstrate that the proposed technique significantly improves the cost of the test in comparison with the best existing test scheduling method.     

可信设计技术的脆弱性分析与防御

片上系统 (SoC) 设计人员通常使用第三方知识产权 (3PIP) 核来实现特定功能。由于这些 3PIP 核不受信任，所搭建的 SoC受到了硬件木马 (HT) 的威胁。作为可信设计技术的一个子集，多样性冗余机制在使用不可信3PIP建立可信计算方面具有较好的应用前景。然而，该文发现通过探索激活序列所设计的硬件木马能够破坏多样性冗余机制的安全性。鉴于此，该文提出一种改进的基于检查点的多样性冗余机制来防御此类攻击。     

Optimization of test resources for 3D SoC based on game theory

The ever-increasing complexity of on-chip interconnection poses great challenges for the architecture of conventional system-on-chip (SoC) in semiconductor industry. The rapid development of process technology enables the creation of stacked 3-dimensional (3D) SoC by means of through-silicon-via (TSV). Stacked 3D SoC testing consists of two major issues, test architecture optimization and test scheduling. This paper proposed game theory based optimization of test scheduling and test architecture to achieve win-win result as well as individual rationality for each player in a game. Game theory helps to achieve equilibrium between two correlated sides to find an optimal solution. Experimental results on handcrafted 3D SoCs built from ITC’2 benchmarks demonstrate that the proposed approach achieves comparable or better test times at negligible computing time.     

Wafer-Level Defect Screening for “Big-D/Small-A” Mixed-Signal SoCs

Product cost is a key driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of “big-D/small-A” mixed-signal system-on-chip (SoC) designs. Packaging cost has recently emerged as a major contributor to the product cost for such SoCs. Wafer-level testing can be used to screen defective dies, thereby reducing packaging cost. We propose a new correlation-based signature analysis technique that is especially suitable for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is used to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss, and packaging costs. Experimental results are presented for a typical mixed-signal “big-D/small-A” SoC, which contains a large section of flattened digital logic and several large mixed-signal cores.      

基于片上网络的系统芯片测试研究

文章介绍了基于片上网络对系统芯片进行测试的原理和实例，这是一种新的设计方法。首先讨论了未来系统芯片存在的各方面测试挑战，并提出了基于片上网络结构的解决方案。其次，在OSI网络堆栈参考模型的基础上．提出了面向测试的片上网络协议堆栈以及对应的测试服务。最后，介绍了基于片上网络的模块化测试方法。