热载流子应力下p-MOSFETs在低栅电压范围的统一退化模型

研究了低栅电压范围的热载流子统一退化模型.发现对于厚氧化层的p-MOSFETs主要退化机制随应力电压变化而变化,随着栅电压降低,退化机制由氧化层俘获向界面态产生转变,而薄氧化层没有这种情况,始终是界面态产生;此外退化因子与应力电压成线性关系.最后得出了不同厚度的p-MOSFETs的统一退化模型,对于厚氧化层,退化由电子流量和栅电流的乘积决定,对于薄氧化层,退化由电子流量决定.     

热载流子应力下p-MOSFETs在低栅电压范围的统一退化模型

研究了低栅电压范围的热载流子统一退化模型.发现对于厚氧化层的p-MOSFETs主要退化机制随应力电压变化而变化,随着栅电压降低,退化机制由氧化层俘获向界面态产生转变,而薄氧化层没有这种情况,始终是界面态产生;此外退化因子与应力电压成线性关系.最后得出了不同厚度的p-MOSFETs的统一退化模型,对于厚氧化层,退化由电子流量和栅电流的乘积决定,对于薄氧化层,退化由电子流量决定.     

基于DCIV法对pMOSFET热载流子损伤的研究

利用新型的直流电流电压(DCIV)法研究了热载流子应力下的亚微米pMOSFET的氧化层陷阱电荷和表面态产生行为,并对热载流子应力下pMOSFET的阈值电压和线性区漏端电流的退化机制做出了物理解释.实验发现在栅极电压较高的热载流子应力条件下,热载流子引发表面态密度随时间变化的两个阶段:第一阶段,电负性的氧化层陷阱电荷起主导作用,使线性区漏端电流随时间增加;第二阶段,表面态逐渐起主导作用,导致线性电流随时间逐渐减小.     

Snapback应力对90nm nMOSFET栅氧化层完整性的影响

基于测试对snapback应力引起的栅氧化层损伤特性和损伤位置进行了研究.研究发现应力期间产生的损伤引起器件特性随应力时间以近似幂指数的关系退化.应力产生的氧化层陷阱将会引起应力引起的泄漏电流增加,击穿电荷减少,也会造成关态漏泄漏电流的退化.栅氧化层损伤不仅在漏区一侧产生,而且也会在源区一侧产生.热空穴产生的三代电子在指向衬底的电场作用下向Si-SiO2界面移动,这解释了源区一侧栅氧化层损伤的产生原因.     

Snapback应力对90nm nMOSFET栅氧化层完整性的影响

基于测试对snapback应力引起的栅氧化层损伤特性和损伤位置进行了研究．研究发现应力期间产生的损伤引起器件特性随应力时间以近似幂指数的关系退化．应力产生的氧化层陷阱将会引起应力引起的泄漏电流增加，击穿电荷减少，也会造成关态漏泄漏电流的退化．栅氧化层损伤不仅在漏区一侧产生，而且也会在源区一侧产生．热空穴产生的三代电子在指向衬底的电场作用下向Si-SiO2界面移动，这解释了源区一侧栅氧化层损伤的产生原因．     

α-Ga2O3基SBD场板结构与电流台阶的关联研究

作为典型的超宽禁带半导体，氧化镓(Ga₂O₃)逐渐以新型功率器件优选材料的身份成为研究热点。近年来它的亚稳态α相因具有相对最宽的带隙，且与蓝宝石、氮化镓相似的六角晶格而受到关注。研究了α-Ga₂O₃基肖特基二极管器件，在TCAD仿真结果中发现反向偏置的I-V特性中出现了电流台阶。通过调节可能影响电流台阶的主要因素：漂移区厚度、掺杂浓度和场板结构，发现击穿特性中的电流台阶随着漂移区厚度的增加而变长，但对掺杂浓度变化的依赖性较弱，解释了漂移区在反偏电场作用下的耗尽过程是电流台阶的产生机制。采用分段场板结构可以优化漂移区的电场分布并提高器件击穿电压，器件击穿的最大电场强度超过10 MV/cm。对电流台阶机制的分析结果有助于抑制器件泄漏电流，提高耐压范围。     

深亚微米NMOSFETs总剂量辐射与热载流子效应研究

本文对深亚微米器件的总剂量辐射与热载流子效应进行了对比试验研究。结果表明虽然总剂量与热载流子效应在损伤原理上存在相似的地方,但两种损伤的表现形式存在明显差异。总剂量辐射损伤主要增加了器件的关态泄漏电流,而热载流子损伤最显著的特点是跨导与输出特性曲线降低。分析认为,STI隔离区辐射感生氧化物正电荷形成的电流泄漏通道是造成总剂量辐射后电流增长的根源,而栅氧化层的氧化物负电荷与栅界面态的形成是造成热载流子退化的原因。因此,对二者进行加固时应侧重于不同的方面。     

0.18微米三重自对准分栅闪存擦除电压对耐久性的影响

本论文对0.18微米三重自对准分栅闪存中擦除电压对耐久性的影响进行了研究。为了得到最好的耐久性,擦除电压需要进行合适的优化。由于隧穿氧化层会在编程/擦除循环过程中产生电荷陷阱并俘获电荷从而降低浮栅电势,过低的擦除电压会增加闪存单元电流对于浮栅电势变化的敏感性,从而造成更严重的耐久性退化。同时,过高的擦除电压会在选择栅氧化层中产生陷阱电荷,从而也会造成更严重的耐久性退化。论文同时提出了一种擦除电压递增的方法并进行了验证。这种方法能够更好地在两种耐久性退化机制之间进行平衡,从而进一步改善耐久性。     

热空穴应力下LDD nMOSFET中GIDL电流退化特性研究*

本文通过GIDL电流参数IDIFF对空穴应力下LDD nMOSFET中的GIDL电流退化进行了深入研究。IDIFF是在相同VDG下漏电压VD=1.4V和栅电压VG=-1.4V两种情形下的GIDL电流之差。空穴陷落在栅漏交叠区的氧化层中导致GIDL电流退化。这些陷落的空穴减小了上述两种对称的测试情形下的横向电场差ΔEX从而使得IDIFF表小。从GIDL电流中提取的IDIFF随着应力时间t的增加而减小。IDIFF的退化量ΔIDIFF,MAX与应力时间成幂指数关系：ΔIDIFF,MAX∝tm, m=0.3. 并用热电子应力实验验证了HHS实验中的相关物理机理。     

1200 V SiC MOSFET重复非钳位感性开关测试的退化机制研究

为了研究1200 V SiC MOSFET在重复非钳位感性开关(Unclamped-Inductive-Switching, UIS)应力下的电学参数退化机制，基于自行搭建的UIS实验平台以及Sentaurus仿真设计工具，首先深入分析了重复UIS测试后器件静态参数与动态参数的退化；接着基于FN隧穿公式对栅极漏电流数据进行拟合，得到随着UIS测试次数增加SiC/SiO₂界面的势垒高度从2.52 eV逐渐降低到2.06 eV;最后解释了SiC MOSFET在重复UIS测试后的电流输运过程。结果表明，在重复雪崩应力的作用下，大量的正电荷注入至结型场效应管区域上方的栅极氧化层中，影响了该区域的电场分布以及耗尽层厚度，导致被测器件(Device Under Test, DUT)的导通电阻、漏源泄漏电流、电容特性等电学参数呈现出不同程度的退化，并且氧化物中的正电荷的积累也使电子隧穿通过栅介质的电流得到了抬升。     

Off-state avalanche breakdown induced degradation in 20 V NLDMOS devices

Degradation behaviors of 20 V NLDMOS operated under off-state avalanche breakdown conditions are presented.A constant current pulse stressing test is applied to the device.Two different degradation mechanisms are identified by analysis of electrical data,technology computer-aided design(TCAD) simulations and charge pumping measurements.The first mechanism is attributed to positive oxide-trapped charges in the N-type drift region,and the second one is due to decreased electron mobility upon interface stat...     

Multiple uniform layer approximation in analysis of negative resistance in p-n junction in breakdown

A simplified analytical method of calculating high-frequency, small signal negative resistance of p-n junctions in breakdown is presented. The negative resistance can lead to microwave oscillations in Impact Avalanche Transit Time (IMPATT) diodes. The method consists in subdividing the entire space charge region into several uniform layers, each of which has constant avalanche multiplication (including zero), and connecting the analytical solutions of the successive layers (multiple uniform layer approximation). The simplest case of the approximation, in which there is only one constant-avalanche region and one or two avalanche-free drift regions, is used to investigate how the small signal characteristics change with width and position of the avalanche region. From the behavior of the small signal negativeQ, it is expected that for low bias currents the oscillator performance improves when the avalanche region becomes relatively shorter, when its position moves from the center to the edge of the space charge region, and when the total space charge layer becomes wider. In materials with larger ionization rates, a negative resistance of a given quality (Q) is obtained at lower breakdown voltage and bias current.     

IMPATT operation below the avalanche frequency

Very high output powers are obtained with double drift IMPATT diodes at current densities which shift the avalanche frequency above the oscillation frequency: 30-40 W pulsed around 90 GHz. This operation mode cannot be explained in terms of the conventional READ theory. A numerical large signal simulation shows that avalanche multiplication over the whole diode takes place. At high current densities the double drift device behaves like a pin diode without the unfavourable breakdown of the ionisation process in the centre of the diode.<>     

Novel edge suppression technique for planar avalanche photodiodes

We present an advanced drift diffusion simulation of the joint opening effect (JOE) avalanche photodiode (APD). The joint opening effect APD is a new design for achieving edge breakdown suppression in planar avalanche photodiodes. It is a single growth process that achieves center breakdown dominance without the use of guard rings, partial charge sheets, or surface etches. The JOE APD only requires the diffusion of the primary well. Edge breakdown suppression is achieved by partially insulating the electric field growth in the active region from the geometry of the primary well     

Conduction current injection delay in Read GaAs IMPATT diodes

We find experimentally that, for GaAs Read avalanche diodes, the optimal drift region width is not simply inversely proportional to optimum frequency. This finding can be understood by noting that the injection phase of the avalanche current into the drift region is not 90° with respect to the voltage maximum, but varies as a function of frequency. The experimental observations are in reasonable agreement with solutions of the Read equation which include the reverse junction saturation current. The theoretical fit to the data is relatively insensitive to the avalanche intrinsic response time, and thus we cannot make an independent determination of its value at present.     

On the signal dependence of avalanche noise generation

The influence of ionization in the drift space of an IMPATT diode on the noise generation in the avalanche process is studied. It is found that carrier generation by ionization in the drift space increases the current minima between the current pulses as generated in the avalanche region. The build-up of new avalanche current pulses therefore starts from a higher current level and consequently the behavior is less noisy. The effect of this decrease in noise on the IMPATT-diode oscillator FM noise is estimated.     

Drain voltage limitations of MOS transistors

A comprehensive investigation has been carried out into the factors which influence the maximum drain voltage of an M.O.S. transistor for normal pentode-like operation. The drain voltage is limited by two principal mechanisms, namely punch-through of the drain depletion region to the source, and breakdown, due to impact ionization in the high field region at the drain edge. A two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through or avalanche breakdown, from a solution of Poisson's equation within the substrate depletion region, is described. The solutions are obtained using finite difference numerical methods which take into account the gate-induced potential profiles at the edge of the source and drain junctions. Boundary conditions of zero effective gate bias and channel current are imposed which simplify the solution of Poisson's equation to an electrostatic one. The punch-through voltage V_PT is defined as the drain-to-source voltage at which the longitudinal field at any point along the edge of the source region inverts in sign to permit the drift of minority carriers from source to drain. Breakdown voltage, V_BD, however, is determined by the drain voltage at which the maximum field in the device reaches the critical value for avalanche multiplication. Good agreement is achieved between theoretical and practical results for both mechanisms on a wide variety of devices. It is shown that V_PT decreases as the channel length and substrate doping concentration decrease and as the oxide thickness and diffusion depth increase. V_BD, however, decreases as the channel length, oxide thickness and diffusion depth decrease.Punch-through and breakdown are discussed for gate bias conditions above and below threshold. The sharp fall in breakdown voltage as the gate bias rises above threshold is explained on the basis of injected charge from the channel into the drain depletion region.     

Surface conduction in short-channel MOS devices as a limitation to VLSI scaling

In MOS VLSI device scaling, two major limiting mechanisms are the punchthrough and source-drain breakdown. The punchthrough mechanism is generally considered a bulk-dominated effect. Drain-source avalanche breakdown is generally attributed to bipolar transistor action between drain and source, dominated by injection through the neutral substrate region. The present work includes an experimental verification and a qualitative model demonstrating that both punchthrough and drain-source avalanche breakdown limitations are surface and surface-depletion-region dominated mechanisms, respectively. The two mechanisms are treated simultaneously since both involve enhanced injection from the source due to drain-induced source-potential barrier lowering. The experimental verification is done over a wide range of relevant device parameters, channel implant concentration between 5 × 10¹⁴-1 × 10¹⁶cm^-3for punchthrough and 2 × 10¹⁵-5 × 10¹⁶cm^-3for drain-source avalanche breakdown, effective channel length of 1.0-30.0 µm for both mechanisms.     

Avalanche breakdown in high-voltage D-MOS devices

A new type of voltage breakdown occurring in high-voltage D-MOS transistors is described. This effect severely reduces the high-voltage capability of these devices when the gate field plate is extended through the drift region toward overlapping the n⁺drain contact region. The breakdown is shown to be due to an avalanche phenomenon appearing close to the n⁺region, due to the very high field induced in this NIOS structure in nonequilibrium. A first-order theory is developed to confirm the conclusions of the experimental study.     

Transient temperature profiles within the active region of uniformly doped and high—Low doped Schottky IMPATT's

Results of an analytical investigation of transient and steady-state temperature and current profiles within the active region of a variety of IMPATT structures are presented. The analyses are based on thermal models which assume power dissipation distributions with an axial dependence proportional to the electric field intensityE(z)and a radial dependence proportional to the local current densityj(r). Examples are presented in which the local current density is assumed to decrease with the local temperature according to the expressionj(r) = a [V - V_{0} - b(T(r) - T_{0})]. The temperature gradients within the active region depend strongly on the doping profile. These analyses show that the maximum temperature at the edge of the active region can be as much as 25 percent higher than at the center of the avalanche region, especially for high-efficiency high-power structures where the ionization is highly localized and the electric-field intensity in the drift region is sufficiently high to prevent unsaturated drift velocities and depletion-layer modulation. Breakdown calculations using temperature-dependent ionization coefficients and axial temperature profiles suggest that actual temperatures within a device can be significantly higher than those measured experimentally by using a predetermined breakdown voltage versus temperature calibration curve. Curves are presented which show normalized current density and axial and radial temperature profiles within the active region of selected devices for various values of time.