一种平衡设计压控振荡器和自动频率校准的快速锁定宽带频率综合器

A wideband fractional-N frequency synthesizer is implemented in a 65 nm CMOS process.It employs a wideband LC voltage-controlled oscillator(VCO) with optimized VCO gain(KVCO/and a sub-band step to improve automatic frequency calibration(AFC) efficiency at negligible expense of phase noise performance.An agile AFC is realized by direct mapping based on the division ratio,and optional redundant counting and comparing calibration is introduced accommodating PVT variations,which samples the reference clock using the prescaled VCO output as a discriminating clock.A charge pump with switched charging current is adopted to compensate for the loop bandwidth variation.Measurement results show this directly-mapped AFC locates the target sub-band in 100 ns and only needs 1.2 s for redundant calibration.The frequency synthesizer spans a frequency range from 0.62 to 1.52 GHz,with phase noise of-86 dBc/Hz at 10 kHz offset and-122 dBc/Hz at 1 MHz offset while consuming 9.76 mA from a 1.2 V supply.     

一个含宽带VCO 和多模正交分频器的可输出220MHz-1100MHz 频率的低噪声频率综合器

This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase(I/Q) signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation(WIA) applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator(VCO) is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 k Hz loop bandwidth, lowest measured phase noise is 106 d Bc/Hz at a 10 k Hz offset and 131 d Bc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 m CMOS process, the synthesizer occupies a chip area of 1.2 mm2, consumes only 15 m W from the 1.8 V power supply,and settles within 13.2 s. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.     

A 5 GHz CMOS frequency synthesizer with novel phase-switching prescaler and high-Q LC-VCO

A phase-locked loop(PLL) frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator(VCO) is presented.The phase-switching prescaler with a novel modulus control mechanism is much more robust on process variations.The Q factor of the inductor,I-MOS capacitors and varactors in the VCO are optimized.The proposed frequency synthesizer was fabricated by SMIC 0.13μm 1P8M MMRF CMOS technology with a chip area of 1150×2500μm~2.When locking at 5 GHz,the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is -122.45 dBc/Hz.     

A 900 MHz fractional-N synthesizer for UHF transceiver in 0.18μm CMOS technology

A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16(24)sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip–flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 k Hz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma–delta modulator is applied. When its relative frequency resolution is settled to 10-6, the testing results show that the phase noises are –120.6 d Bc/Hz at 1 MHz and –95.0 d Bc/Hz at 100 k Hz. The chip is2.1 mm2 in UMC 0.18μm CMOS. The power is 36 m W at a 1.8 V supply.     

具有自校准压控振荡器和精确自动频率校准算法的低噪声频率合成器

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.     

一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.     

A 4.8GHz CMOS Fully Integrated LC Balanced Oscillator with Symmetrical Noise Filter Technique and Large Tuning Range

This paper presents a fully integrated 4.8GHz VCO with an invention——symmetrical noise filter technique.This VCO,with relatively low phase noise and large tuning range of 716MHz,is fabricated with the 0.25μm SMIC CMOS process.The oscillator consumes 6mA from 2.5V supply.Another conventional VCO is also designed and simulated without symmetrical noise filter on the same process,which also consumes 6mA current and is with the same tuning.Simulation result describes that the first VCO’ phase noise is 6dBc/Hz better than the latter’s at the same offset frequency from 4.8GHz.Measured phase noise at 1MHz away from the carrier in this 4.8GHz VCO with symmetrical noise filter is －123.66dBc/Hz.This design is suitable for the usage in a phase-locked loop and other consumer electronics.It is amenable for future technologies and allows easy porting to different CMOS manufacturing process.     

A constant loop bandwidth fractional-N frequency synthesizer for GNSS receivers

正A constant loop bandwidth fractional-TV frequency synthesizer for portable civilian global navigation satellite system(GNSS) receivers implemented in a 130 nm 1P6M CMOS process is introduced.Via discrete working regions,the LC-VCO obtains a wide tuning range with a simple structure and small VCO gain.Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps.The optimized bandwidth is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies.Measurement results show that this synthesizer attains an in-band phase noise lower than -93 dBc at a 10 kHz offset and a spur less than -70 dBc;the bandwidth varies by±3%for all the GNSS signals.The whole synthesizer consumes 4.5 mA current from a 1 V supply,and its area(without the LO tested buffer) is 0.5 mm~2.     

采用PMOS底部电流源的低功耗电流自调整压控振荡器

This paper presents the design and implementation of a current self-adjusted VCO with low power consumption. In the proposed VCO, a bottom PMOS current source instead of a top one is adopted to decrease the tail noise. A current self-adjusted technique without additional external control signals is taken to ensure the VCO starts up in the whole band while keeping the power consumption relatively low. Meanwhile, the phase noise of the VCO at the low frequency （high Cvar） can be reduced by the technique. The circuit is implemented in 0.18 μm CMOS technology. The proposed VCO exhibits low power consumption of 〈1.6 mW at a 1.5 V supply voltage and a tuning range from 11.79 to 12.53 GHz. The measured phase noise at 1 MHz offset from the frequency 11.79 GHz is-104.7 dBc/Hz, and the corresponding FOM is -184.2 dBc/Hz.     

应用于60-GHz无线通信的全差分锁相环频率综合器

A 40-GHz phase-locked loop(PLL) frequency synthesizer for 60-GHz wireless communication applications is presented. The electrical characteristics of the passive components in the VCO and LO buffers are accurately extracted with an electromagnetic simulator HFSS. A differential tuning technique is utilized in the voltage controlled oscillator(VCO) to achieve higher common-mode noise rejection and better phase noise performance. The VCO and the divider chain are powered by a 1.0 V supply while the phase-frequency detector(PFD)and the charge pump(CP) are powered by a 2.5 V supply to improve the linearity. The measurement results show that the total frequency locking range of the frequency synthesizer is from 37 to 41 GHz, and the phase noise from a 40 GHz carrier is –97.2 d Bc/Hz at 1 MHz offset. Implemented in 65 nm CMOS, the synthesizer consumes a DC power of 62 m W, including all the buffers.     

On Faster I DDQ Measurements

The purpose of this paper is to introduce a new I _DDQ measurement technique based on active successive approximations, called ASA-I _DDQ. This technique has unique features facilitating a speed-up in I _DDQ measurement. Experimental results suggest that a significant speed-up factor (up to 4) can be obtained over the QuiC-Mon technique. Such a speed-up is a key element in the replacement of single-threshold I _DDQ testing since it amplifies the effectiveness of post-processing techniques.     

Performance analysis of 20 nm gate-length In0.2Al0.8N/GaN HEMT with Cu-gate having a remarkable high ION/IOFF ratio

Abstract： We propose a new structure of InxAll-xN/GaN high electron mobility transistor （HEMT） with gate length of 20 nm. The threshold voltage of this HEMT is achieved as -0.472 V. In this device the InA1N barrier layer is intentionally n-doped to boost the ION/IOFF ratio. The InAlN layer acts as donor barrier layer for this HEMT which exhibits an ION = 10-4.3 A and a very low IOFF = 10-14.4 A resulting in an ION/IoFF ratio of 1010.1. We compared our obtained results with the conventional InAlN/GaN HEMT device having undoped barrier and found that the proposed device has almost l0s times better ION/IOFF ratio. Further, the mobility analysis in GaN channel of this proposed HEMT structure along with DC analysis, C-V and conductance characteristics by using small-signal analysis are also presented in this paper. Moreover, the shifts in threshold voltage by DIBL effect and gate leakage current in the proposed HEMT are also discussed. InAlN was chosen as the most preferred barrier layer as a replacement of AlGaN for its excellent thermal conductivity and very good scalability.     

New op-amp-RC to G m -C transformation method

A new transformation method is proposed and used to transform op-amp-RC circuits to G _m -C ones with only grounded capacitors. The proposed method enables the generation of high-performance G _m -C filters that benefit from the advantages of good and well-known op-amp-RC structures and at the same time feature electronic tunability, high frequency capability and monolithic integration ability. An attractive feature of the proposed method is that it results in G _m -C structures with only grounded capacitors in spite of the presence of floating capacitors in the original op-amp-RC circuits. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964, the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA, U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997–September 2003, Dr. Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985–1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987–1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo. He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In November 2005, Dr. Soliman gave a lecture at Nanyang Technological University, Singapore. Dr. Soliman was also invited to visit Taiwan and gave lectures at Chung Yuan Christian University and at National Central University of Taiwan. In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr. Soliman is a Member of the Editorial Board of the IEE Proceedings Circuits, Devices and Systems. Dr. Soliman is a Member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Dr. Soliman served as Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters) from December 2001 to December 2003 and is Associate Editor of the Journal of Circuits, Systems and Signal Processing from January 2004–Now.     

Preparation and Thermoelectric Properties of Ag<Subscript>0.5</Subscript>In<Subscript>0.5−<Emphasis Type="Italic">x</Emphasis></Subscript>Pb<Subscript>5</Subscript>Sn<Subscript>4</Subscript>Te<Subscript>10</Subscript>

A series of compounds with composition Ag_0.5In_0.5−x Pb₅Sn₄Te₁₀ (x = 0.05 to 0.20) were prepared by slowly cooling the melts of the corresponding elements, and the effect of In content on the thermoelectric transport properties of these compounds has been investigated. Results indicate that the compounds’ electronic structure is sensitive to In content, and that the carrier concentration of these compounds at room temperature increases from 4.86 × 10¹⁸ cm⁻³ to 3.85 × 10²¹ cm⁻³ as x increases from 0.05 to 0.20. For these compounds, electrical conductivity decreases and Seebeck coefficient increases with increasing In content. Ag_0.05In_0.03Pb_0.5Sn_0.4Te₁₀ shows very low lattice thermal conductivity, and has a maximum dimensionless figure of merit ZT of 1.2 at 800 K.     

CH3NH3PbI3/p-Si异质结的光电特性研究

利用一步溶液法在p型Si衬底上生长有机/无机杂化钙钛矿CH3NH3PbI3薄膜,构成CH3NH3PbI3/p-Si异质结。利用原子力显微镜(AFM)、扫描电子显微镜(SEM)对薄膜形貌和结构进行表征,通过无光照和有光照条件下的电流-电压(I-V)、电容-电压(C-V)测试对异质结的光电特性进行研究。I-V测试结果显示CH3NH3PbI3/p-Si异质结具有整流特性,正反偏压为±5V时,整流比大于70,并在此异质结上观察到了光电转换现象,开路电压为10mV,短路电流为0.16uA。C-V测试结果显示Ag/CH3NH3PbI3/p-Si异质结具有与MIS(金属-绝缘层-半导体)结构相似的C-V特性曲线,与理想MIS的C-V特性曲线相比,异质结的C-V曲线整体沿电压轴向正电压方向平移。C-V特性曲线的这种平移表明Ag/CH3NH3PbI3/p-Si异质结界面存在界面缺陷,CH3NH3PbI3层也可能存在固定电荷。这种界面缺陷是导致CH3NH3PbI3/p-Si异质结开路电压的大幅度降低的重要原因。此外,CH3NH3PbI3薄膜的C-V测试结果显示其具有介电非线性特性,其介电常数约为4.64。     

改进碲镉汞液相外延方法原位生长正组分梯度薄膜材料

研究了液相外延生长条件对碲镉汞薄膜材料组分梯度的影响,建立了指导液相外延生长的理论模型。通过改变水平推舟液相外延工艺的汞损失速率,生长出具有正组分梯度的碲镉汞薄膜材料。针对这种特定条件下生长的碲镉汞外延薄膜,通过腐蚀减薄光谱测试与二次离子质谱测试证实了材料具有正组分梯度结构。与传统方法生长的具有负组分梯度的碲镉汞薄膜相比,这种薄膜材料具有相近的表面形貌与红外透射光谱曲线;且具有较高的晶体质量,其X射线衍射双晶摇摆曲线半峰宽达到28.8 arcsec。     

Performance improvement of c-Si solar cell by a combination of SiNx/SiOx passivation and double P-diffusion gettering treatment

SiN_x/SiO_x passivation and double side P-diffusion gettering treatment have been used for the fabrication of c-Si solar cells. The solar cells fabricated have high open circuit voltage and short circuit current after the double P-diffusion treatment. In addition to better surface passivation effect, SiN_x/SiO_x layer has lower reflectivity in long wavelength range than conventional SiN_x film. As a consequence, such solar cells exhibit higher conversion efficiency and better internal quantum efficiency, compared with conventional c-Si solar cells.     

Partial Fraction Decomposition and Correlation Sequence in 2D Systems

In this paper, results of the one-dimensional (1D) digital filtering are extended to the two-dimensional (2D) case. It introduces a technique and an algorithm for the computation of the product H(z₁,z₂)H(z₁⁻¹,z₂⁻¹). The technique is used to find a minimum phase transfer function of a 2D system such that the previous product matches a given correlation sequence. The algorithm requires less arithmetic operations than the traditional methods. The former is based on a matrix formulation of the product, which is used to investigate the 2D partial fraction decomposition (PFD) and stability.     

微波法制备高活性H1-xSr2Nb3-xMoxO10 (x = 0, 0.05, 0.1, 0.15 and 0.2) 光催化剂

通过微波辅助法制备出高活性H1-xSr2Nb3-xMoxO10光催化材料,制备过程和时间均被大大缩短。采用X射线粉末衍射（XRD）、扫描电镜（SEM）、紫外-可见吸收吸收光谱（UV-Vis DRS）等表征其材料性能。考察了催化材料在40W汞灯辐照下催化降解甲基橙的催化性能。实验结果表明,MoO3的掺入量为15%（摩尔分数）时,材料的光催化性能最优。     

Etch damage evaluation on (Bi4−xLax)Ti3O12 thin films during the etch process using inductively coupled plasma sources

The etching mechanism of (Bi_4−xLa_x)Ti₃O₁₂ (BLT) thin films in Ar/Cl₂ inductively coupled plasma (ICP) and plasma-induced damages at the etched surfaces were investigated as a function of gas-mixing ratios. The maximum etch rate of BLT thin films was 50.8 nm/min of 80% Ar/20% Cl₂. From various experimental data, amorphous phases on the etched surface existed on both chemically and physically etched films, but the amorphous phase was thicker after the 80% Ar/20% Cl₂ process. Moreover, crystalline “breaking” appeared during the etching in Cl₂-containing plasma. Also the remnant polarization and fatigue resistances decreased more for the 80% Ar/20% Cl₂ etch than for pure Ar plasma etch.