SiGe HBT发射极延迟时间模型

在对SiGe HBT(异质结双极晶体管)载流子输运的研究基础上,建立了包括基区扩展效应SiGe HBT发射极延迟时间τe模型.发射极延迟时间与发射结势垒电容和集电结势垒电容密切相关.在正偏情况下,通常采用的势垒区耗尽层近似不再适用,此时需要考虑可动载流子的影响.本文重点分析了电流密度及发射结面积等参数对SiGe HBT发射极延迟时间的影响.     

SiGe HBT发射极延迟时间模型

在对SiGe HBT（异质结双极晶体管）载流子输运的研究基础上,建立了包括基区扩展效应SiGe HBT发射极延迟时间τe模型．发射极延迟时间与发射结势垒电容和集电结势垒电容密切相关．在正偏情况下,通常采用的势垒区耗尽层近似不再适用,此时需要考虑可动载流子的影响．本文重点分析了电流密度及发射结面积等参数对SiGe HBT发射极延迟时间的影响．     

低温高注入硅双极晶体管电流增益的定量模拟

本文考虑了基区复合电流，发射结空间电荷区复合电流，基区高注入引起的禁带变窄效应，Ｅａｒｌｙ效应，基区和发射区电导调制效应，有效基区展宽效应以及发射区电流集边效应，定量地模拟了硅双极晶体管电流增益在７７Ｋ和３００Ｋ时与集电极电流的关系，并且与实验结果相吻合，计算还表明在低温７７Ｋ时，电流增益的大注入效应由基区电导调制效应和发射区电流集边效应决定，而在３００Ｋ时则由有效基区展宽效应决定。     

低温高注入硅双极晶体管电流增益的定理模拟

本文了基区复合电流，发射结空间电荷区复合电流，基区高主入引起的禁带变窄效应，Ｅａｒｌｙ效应，基区和发射区电导调制效应，有效基区展宽效应以及发射区电流集边效应，定量地模拟了硅双极晶体管电流增益在７７Ｋ和３００ｋ时与集电极电流的关系，并且与实验结果相吻合。     

InGaAsP/InP异质结双极晶体管的研究

用液相外延方法研制了InGaAsP/InP异质结双极晶体管(HBT),并研究了其直流特性。该HBT的发射区和集电区材料为InP(禁带宽度为1.35eV),基区材料为InGaAsP(禁带宽度0.95eV)。器件采用台面结构,发射结、集电结面积分别为5.0×10~(-5)cm~2、3.46×10~(-5)cm~2。基区宽度约为0.2μm,基区掺杂浓度为(2～3)×10~(17)/cm~3。在I_c=3～5mA,V_(ce)=5～10V时。共射极电流放大倍数达到30～760。符号表 q 电子电荷ε介电常数 k 玻耳兹曼常数 T 绝对温度β共射极电流放大倍数γ发射极注入效率 A_e 发射结面积 I_(ne) 发射极电子电流 I_(pe) 发射极空穴电流 I_(rb) 基区体内复合电流 I_(gre) 发射结空间电荷区产生-复合电流 I_(sb) 基区表面复合电流 I_(nc) 被集电极收集的电子电流 m_(pb)~* 基区中空穴有效质量 m_(?)~* 发射区电子有效质量 N_(Ab) 基区中受主掺杂浓度 N_(D(?)) 发射区施主掺杂浓度 N_(D(?)) 集电区施主掺杂浓度 W_b 基区宽度 L_(ab) 基区中电子扩散长度μ_(ab) 基区中电子迁移率τ_(ab) 基区中电子寿命 V_(no) 从发射区注入到基区电子的平均速度 V_(p(?)) 从基区注入到发射区空穴的平均速度△E_g 发射区与基区的禁带宽度差△E_c 异质结交界面导带不连续量△E_v 异质结交界面价带不连续量。且有:△E_c+△E_v=△E_g A_(?) 基区表面有效复合面积     

SiGe异质结晶体管频率特性模型研究

在分析载流子输运和分布的基础上，建立了SiGe异质结晶体管(HBT)各时间常数模型；在考虑发射结空间电荷区载流子分布和集电结势垒区存在可劝电荷的基础上，建立了SiGe HBT发射结势垒电容模型和不同电流密度下包括基区扩展效应的集电结势垒电容模型。对SiGe HBT特征频率及最高振荡频率与电流密度、Ge组分、掺杂浓度、结面积等之间的关系进行了模拟，对模拟结果进行了分析和讨论。     

包含电流集边效应的矩形双极晶体管噪声的精确分析

本文介绍的矩形双极晶体管噪声的精确分析是应用集合近似法(col-lective approach)和输运噪声理论的分析模型推导出来的。在此模型中,考虑了发射极电流集边效应,并精确地描述了中等和低值源阻抗时的噪声性能。确定了等效集总电路的结构,给出在电流和频率的分布范围内表征元件的解析关系。指出:(a)有源基区必须由一般热噪声源的非线性阻抗来表示;(b)对于低源阻抗,散粒噪声发生器的等效输入电压高于由低注入理论所预言的输入电压。而且发现,发射极集边导致:(a)基区阻抗;(b)热噪声;(c)等效集总电路的散粒噪声发生器之间的相互关系均匀而显著地减少。最后,可以看出,在高源阻抗偏置的晶体管中,集边效应产生时,经典的低注入理论似乎是正确的。     

用简化的计算机分析研究双极晶体管的周界注入效应

用可变的周界区域逼近法,以及用园柱形近似把少数载流子电流表示为径向电流之和来研究双扩散双极晶体管自发射极周界向基区的注入效应。综合上述结果与有源基区(即发射极下面的部分)的结果,看到,通过引进周界基区中的电荷和电流,可改进h_(FE)和f_T随I_C变化关系的预测。所用方法的优点为:1)便于快速计算,2)把有源区和周界的基区分开,并提出一种依据制造数据设计器件时改进精度的好方法。     

测定亚微米发射极条宽晶体管物理参数和几何参数

介绍了一种测定亚微米发射极条晶体管的物理参数和几何参数的简便分析方法。该分析方法是为 CG41微波低噪声晶体管的研制而研究的。根据 Gummel 方程得出了用常数和可测量表示的基区平均掺杂浓度(?)_B的表达式。使用简化的 f_T 表达式,通过测量,f_T 与 I_E 的关系确定出基区宽度W_B 以及发射极正向电容 C_E。通过(?)_B、W_B 以及 C_E 的测定,可确定出晶体管的本征基区薄层电阻 R_口_(in)、发射极面积 A_E 和发射极条宽 d_E。应用上述参量的实测值,计算了晶体管的噪声系数 NFc,其结果与实测的噪声系数 NF_m 很一致。     

二维非等温的分布晶体管模型

本文提出了一个考虑了晶体管热电反馈效应的分布晶体管直流模型,称之为“二维非等温的分布晶体管模型”. 本模型考虑了基区高注入效应、Kirk效应以及由内基区电阻、发射极金属化电极薄层电阻所引起的电流横向及纵向集边效应,并计入了晶体管内温度分布的不均匀性对上述诸效应的影响. 借助计算机,利用下降法求解了描述本模型热电特性的非线性方程组,计算结果给出了晶体管发射区内温度、电流的二维分布数值,从而得到了晶体管热电反馈效应的定量描述,且理论结果与实验吻合良好. 利用本模型可进行功率晶体管的计算机辅助设计,预测功率晶体管的安全工作区并指导器件的可靠性设计.     

Leakage current mechanisms in SiGe HBTs fabricated using selectiveand nonselective epitaxy

SiGe heterojunction bipolar transistors (HBTs) have been fabricated using selective epitaxy for the Si collector, followed in the same growth step by nonselective epitaxy for the p⁺ SiGe base and n-Si emitter cap. DC electrical characteristics are compared with cross-section TEM images to identify the mechanisms and origins of leakage currents associated with the epitaxy in two different types of transistor. In the first type, the polysilicon emitter is smaller than the collector active area, so that the extrinsic base implant penetrates into the single-crystal Si and SiGe around the perimeter of the emitter and the polycrystalline Si and SiGe extrinsic base. In these transistors, the Gummel plots are near-ideal and there is no evidence of emitter/collector leakage. In the second type, the collector active area is smaller than the polysilicon emitter, so the extrinsic base implant only penetrates into the polysilicon extrinsic base. In these transistors, the leakage currents observed depend on the base doping level. In transistors with a low doped base, emitter/collector and emitter/base leakage is observed, whereas in transistors with a high doped base only emitter/base leakage is observed. The emitter/collector leakage is explained by punch through of the base caused by thinning of the SiGe base at the emitter perimeter. The emitter/base leakage is shown to be due to a Poole-Frenkel mechanism and is explained by penetration of the emitter/base depletion region into the p⁺ polysilicon extrinsic base at the emitter periphery. Variable collector/base reverse leakage currents are observed and a variety of mechanisms are observed, including Shockley-Read-Hall recombination, trap assisted tunneling, Poole-Frenkel and band to band tunneling. These results are explained by the presence of polysilicon grains on the sidewalls of the field oxide at the collector perimeter     

The effects of distributed base potential on emitter-current injection density and effective base resistance for stripe transistor geometries

Simple analytic expressions are derived for the variation of base current, emitter current and emitter-base voltage along the emitter junction of a transistor structure due to the flow of dc base current parallel to the emitter junction. The effective width of the emitter region is discussed, and it is shown that as the emitter width is increased, the effective emitter width approaches a constant value. The change in base resistance with emitter current is also calculated. The use of base contacts on each side of an emitter region is discussed and the analysis is shown to be applicable to this problem for equal or unequal division of base current between the two contacts. The results are applied to a planar transistor structure.     

Characterisation of emitter/base leakage currents in SiGe HBTs produced using selective epitaxy

SiGe heterojunction bipolar transistors have been fabricated using selective epitaxy for the Si collector, followed in the same growth step by non-selective epitaxy for the SiGe base and Si emitter cap. E/B leakage currents are compared with cross-section TEM images to identify sources of leakage currents associated with the epitaxy. In addition, the influence of the position of the extrinsic base implant with respect to the polysilicon emitter on the leakage currents is studied. The emitter/base leakage currents are modelled using Shockley–Read–Hall recombination, trap-assisted tunnelling and Poole–Frenkel (PF) generation. The position of the extrinsic base implant is shown to have a strong influence on the leakage currents. The PF effect dominates the emitter/base leakage current in transistors in which the collector area is smaller than the polysilicon emitter. This result is explained by penetration of the emitter/base depletion region into the p⁺ polysilicon extrinsic base at the perimeter of the emitter. These leakage currents are eliminated when the collector area is increased so that the extrinsic base implant penetrates into the single-crystal silicon at the perimeter of the emitter.     

Optimization of emitter cap growth conditions for InGaP/GaAs HBTs with high current gain by LP-MOCVD

The effect of emitter cap growth conditions on the common-emitter current gain of InGaP/GaAs HBTs, grown by LP-MOCVD, has been studied. This work shows that the material quality of a carbon-doped base is highly dependent on the emitter cap growth. The emitter cap growth effectively serves as a source of thermal stress. This stress on the base during the emitter and cap growth causes the formation of carbon-related defects in the base that increase the base recombination and reduces the current gain. Atomic force microscopy is used to identify these carbon-related defects. Gain improvements of about 40% have been achieved by optimizing the emitter cap growth conditions to reduce the thermal stress.     

On the sidewall effects in submicrometer bipolar transistors

The influence of the emitter sidewall on the dc base and collector current in submicrometer bipolar devices is investigated. Analytical calculations on a simplified two-dimensional transistor model as well as numerical calculations on a more realistic structure show that the two-dimensional nature of the carrier injection into the base and emitter regions near the sidewall can strongly affect the base and collector current. From this analysis it follows that when the emitter width is in the range of the characteristics diffusion length in the emitter or smaller, the base current through the bottom part of the emitter-base junction is strongly diminished when compared with the one-dimensional solution. For shallow emitters the base current through the sidewall strongly depends on the surface-recombination velocity and on the distance between the emitter contact edge and the sidewall junction. The collector current flows mainly through the bottom part of the emitter-base junction. Device design implications are briefly discussed.     

High-low polysilicon-emitter SiGe-base bipolar transistors

Self-aligned heterojunction bipolar transistors with a high-low emitter profile consisting of a heavily doped polysilicon contact on top of a thin epitaxial emitter cap have been fabricated. The low doping in the single-crystal emitter cap allows a very high dopant concentration in the base with low emitter-base reverse leakage and low emitter-base capacitance. The thin emitter cap is contacted by heavily doped polysilicon to reduce the emitter resistance, the base current, and the emitter charge storage. A trapezoidal germanium profile in the base ensures a small base transit time and adequate current gain despite high base doping. The performance potential of this structure was simulated and demonstrated experimentally in transistors with near-ideal characteristics, very small reverse emitter-base leakage current, and 52-GHz peak f_max, and in unloaded ECL and NTL ring oscillators with 24- and 19-ps gate delays, respectively     

A method for determining the emitter and base lifetimes in p-n junction diodes

A method is described that provides an experimental means for the first time to separate and determine the emitter and base lifetimes in a p-n diode after the junction has been fabricated. In the method, several static and transient measurements are analyzed using physical models of the diode characteristics. To illustrate the method, diffused silicon diodes are fabricated having substrate (base) impurity concentrations ranging from 10¹⁴to nearly 10¹⁷phosphorous atoms per cubic centimeter. The results show an emitter lifetime that is much smaller than the base lifetime in the diode having the highest base doping concentration. In this diode, the recombination current from the emitter is 65 percent of the recombination current from the base, demonstrating the significance of the emitter in governing the static current-voltage dependence. The importance of emitter recombination to the transient characteristics is also demonstrated. The paper emphasizes the techniques by which the base and emitter lifetimes are distinguished. It also demonstrates the need for carefully basing the quantitative analysis of the measurements on the underlying diode physics. The method described here applies not only to p-n diodes but also to junction solar cells and transistors.     

Effects of dislocations in silicon transistors with implanted emitters

Silicon bipolar transistors have been made by substituting a shallow phosphorus implanation for the standard emitter deposition used in the manufacture of linear integrated circuits. The implantation was followed by a high temperature heat treatment (drive-in), which caused the implanted ions to diffuse deeper into the semiconductor to give emitter/base junction depths of typically 1.8 μm. When the high temperature heat treatment was performed in an oxidising atmosphere, the resulting transistors had lower gains and higher emitter/base leakages than the comparable standard diffused transistors. However, if an 1180°C drive-in, in an inert atmosphere, was performed prior to the oxidation drive-in, high gains and low emitter/base leakages were obtained. Alternatively, if the oxidation drive-in was omitted, and instead an inert drive-in performed at any temperature between 1000 and 1180°C, high gains and low emitter/base leakages were again obtained. Etching and TEM studies revealed that the low gains and high emitter/base leakages were again obtained. Etching and TEM studies revealed that the low gains and high emitter/base leakages were caused by emitter edge dislocations intersection the emitter/base junction around the perimeter of the emitter. A mechanism is suggested to describe the formation of the emitter edge dislocations.     

Effects of rapid thermal processing on the current gain and emitterresistance of polysilicon emitter bipolar transistors

Results of measurements of base current and emitter resistance of polysilicon emitter transistors subjected to different rapid thermal anneal processes of the interfacial layer and different emitter drive-in times are presented. It is shown that a rapid thermal anneal for temperatures on the order of 1050°C leads to devices in which the base current is essentially independent of the emitter drive-in time. The emitter resistance obtained in devices given this interface anneal is considerably lower than that in devices without the anneal, and hence the values obtained are compatible with the requirements for realizing submicrometer bipolar circuits     

Edge injection and pinch-in effect of transistors with cylindrical geometry

Simple analytical expressions are derived for the variation of the emitter current density along the emitter junction of a transistor with cylindrical geometry due to the flow of the base current parallel to the emitter junction. Depending on the sign of the base current, the emitter injects predominantly either on the edge or in the centre of the junction.