一种新的相位开关实现技术及其在射频双模预分频器中的应用

提出了一种新的相位开关实现技术.基于这种技术设计了一个2/3分频器单元,该单元结构简单,工作频率高,功耗低.为了验证该技术,采用0.25μm CMOS数字工艺实现了一个128/129双模预分频器.对该芯片的测试结果表明其能正确工作于GHz频率范围.当工作频率为2.3GHz时,它消耗的电流仅为13.5mA(2.5V电源电压),芯片面积为0.47mm×0.47mm.     

高速低功耗自适应可编程分频器

在约翰逊计数分频器的基础上,设计了一款双级结构分频器,采用系数自适应分配技术,显著提升了分频器的工作频率,并有效降低功耗。基于45nm CMOS工艺进行仿真,结果表明:该分频器最高工作频率可达8GHz,在1GHz时,49分频的双级可编程分频器功耗仅为63μW,在8GHz时,功耗为312μW。与典型的约翰逊结构相比,双级分频器工作频率可提升1.6倍,在分频器系数设置为6时,最大功耗优化比达到51.82%。     

一种宽分频范围的CMOS可编程分频器设计

设计了一种基于双模预分频的宽范围可编程分频器。对预分频器的逻辑电路进行了改进,提高了最高工作频率,同时,引入输入缓冲级,增加了低频时分频器的输入敏感性。基于Chartered 0.25μm厚栅CMOS工艺,在SpectreRF中仿真,分频器可在50MHz～2.2GHz频率范围正常工作。流片测试结果表明,该分频器可正常工作在作为数字电视调谐芯片本振源的PLL中,对80～900MHz的VCO输出信号,实现256～32767连续分频。     

16 GHz CMOS 4:1分频器

采用TSMC 1.18 μm标准CMOS工艺实现了一种4:1分频器.测试结果表明,电源电压1.8 V,核心功耗18 mW.该分频器最高工作频率达到16 GHz.当单端输入信号为-10 dBm时,具有5.8 GHz的工作范围.该分频器可以应用于超高速光纤通信以及其它高速数据传输系统.     

WSN射频芯片中6GHz RF CMOS低功耗双模前置分频器的设计

介绍了一种可以应用在无线传感网射频芯片中的超高速、低功耗32/33双模前置分频器的内部结构、电路设计原理以及版图设计.该前置分频器采用0.18 μm RF CMOS工艺制作,工作频率范围为1～6 GHz,工作温度范围为-20～+80℃,在I.8 V电压下正常工作频率为4.8 GHz,最高工作频率达到6 GHz,电源电流为2.5 mA,满足系统指标要求.     

10～37 GHz CMOS四分频器的设计

给出基于0.13μm CMOS工艺、采用单时钟动态负载锁存器设计的四分频器.该四分频器由两级二分频器级联而成,级间采用缓冲电路实现隔离和电平匹配.后仿真结果表明其最高工作频率达37 GHz,分频范围为27 GHz.当电源电压为1.2 V、工作频率为37 GHz时,其功耗小于30 mW,芯片面积为0.33×0.28 mm2.     

适用于半速率CDR改进型VCO的设计与实现

在0.13μm数字CMOS工艺下设计实现了一种改进型的差分振荡器电路,该电路采用四级环形结构,其中心工作频率为1.25 GHz,版图面积为50μm×50μm,工作范围1.1～1.4 GHz,VCO的增益约为300 MHz/V,在1.2 V电源电压下、工作频率为1.25 GHz时的平均功耗约为10 mW.版图后模拟结果表明,该VCO输出的四相时钟信号间隔均匀,占空比接近50%,可适用于基于PLL的2.5 Gbps的半速率时钟数据恢复电路.     

一种1.8 V 4.8 GHz 0.9 mW 0.18 μm CMOS分频器

给出了一个电源电压为1.8 V、功耗为0.9 mW的4.8 GHz二分频器。该分频器采用基于反转触发器(TFF)的电路结构,使用动态负载,输出I、Q两路正交信号。对设计的电路采用标准UMC 0.18μm CMOS工艺进行了仿真,结果表明,该分频器工作频率可达6.5 GHz。     

一种超低功耗5 GHz双模预置分频器

介绍了一种改进型的超高速、低功耗双模预置分频器(÷64/65、÷128/129)。该预置分频器采用0.35μm BiCMOS工艺制作,在3.5 V电源电压下最高工作频率达5 GHz,电源电流为4mA,电源电压3.3 V时最高工作频率达4.8 GHz。预置分频器工作在0.5~5 GHz频率范围内输入灵敏度小于-20 dBm,工作在-55~125℃温度范围,最高频率达4.5 GHz。     

低功耗可编程吞脉冲计数器设计

介绍了一种基于0.18μm CMOS工艺的频率合成器子电路吞脉冲计数器的设计方法,并对电路功耗进行了优化.仿真结果表明,该计数器可与双模预分频器构成分频比连续变化的可变分频器,系统最高工作频率为7.5GHz,双模预分频器为采用相位切换结构的16/17预分频器,吞脉冲计数器部分最高工作频率为700MHz,电源电压2V,消耗电流小于0.4mA.     

Fully integrated low phase noise multi-band LC-tank voltage controlled oscillator with switched-capacitor resonator

This paper presents the design and implementation of a fully integrated low noise multi-band LC-tank voltage-controlled-oscillator(VCO).Multi-band operation is achieved by using switched-capacitor resonator.Additional three-bit binary weighted capacitor array is also used to extend frequency tuning range in each band.To lower phase noise,two noise filters are added and a linear varactor is adopted.Implemented in a 0.18 μm complementary-metal-oxide-semiconductor(CMOS) process,the VCO achieves a frequency tuning range covering 2.26～2.48 GHz,2.48～2.78 GHz,2.94～3.38 GHz,and 3.45～4.23 GHz while occupies a chip area of 0.52 mm2.With a 1.8 V power supply,it draws a current of 10.9 mA,10.6 mA,8.8 mA,and 6.2 mA from the lowest band to the highest band respectively.The measured phase noise is-109～-120 dBc/Hz and-121～-131 dBc/Hz at a 1 MHz and 2.5 MHz offset from the carrier,respectively.     

Rotary traveling-wave oscillator design using 0.18 μm CMOS

A rotary traveling-wave oscillator (RTWO) targeted at 5.8 GHz band operation is designed and fabricated using standard 0.18 μm CMOS technology. Both simulation and measurement results are presented. The chip size including pads is 1.5 × 1.5 mm2. The measured output power at a frequency of 5.285 GHz is 6.68 dBm, with a phase noise of-102 dBc/Hz at 1 MHz offset from the carrier.     

一种高分辨率∑△小数分频频率合成器

提出了一种采用新型分频器的小数分频频率合成器。该频率合成器与传统的小数分频频率合成器相比具有稳定时间快、工作频率高和频率分辨率高的优点。设计基于TSMC0.25μm2.5V1P5MCMOS工艺,采用sig-ma-delta调制的方法实现。经测量得到该频率合器工作频率在2.400～2.850GHz之间,相位噪声低于-95dBc/Hz@100kHz,最小频率步进小于30Hz,开关时间小于50μs,满足多数无线通信系统的要求。     

A 4 GHz quadrature output fractional-N frequency synthesizer for an IR-UWB transceiver

This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver.Designed in a 0.18μm mixed-signal & RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order ∑-△ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8° respectively. The measured phase noise is -116 dBc/Hz at 3 MHz offset for a 4 GHz output.Measured spurious tones are lower than -60 dBc. The settling time is within 80 μs. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.     

4.2GHz 1.8V CMOS LC压控振荡器

基于Hajimiri提出的VCO相位噪声模型,分析了差分LC VCO电路参数对于相位噪声的影响。根据前面的分析,详细介绍了LC VCO电路的设计方法:包括高Q值片上电感的设计、变容MOS管的设计以及尾电流的选取。采用SMIC 0.18μm 1P6 M、n阱、混合信号CMOS工艺设计了一款4.2GHz 1.8V LC VCO。测试结果表明:当输出频率为4.239GHz时,频偏1MHz处的相位噪声为-101dBc/Hz,频率调节范围为240MHz。     

带有ESD保护,900MHz/2.4GHz Dual-Band CMOS LNA的设计

设计了一个可以同时工作在900 MHz和2.4 GHz的双频带(Dual-Band)低噪声放大器(LNA).相对于使用并行(parallel)结构LNA的双频带解决方案,同时工作(concurrent)结构的双频带LNA更能节省面积和减少功耗.此LNA在900MHz和2.4 GHz两频带同时提供窄带增益和良好匹配.该双频带LNA使用TSMC 0.25 μm 1P5M RF CMOS工艺.工作在900MHz时,电压增益、噪声系数(Noise Figure)分别是21 dB、2.9 dB;工作在2.4 GHz时,电压增益、噪声系数分别是25dB、2.8 dB,在电源电压为2.5 V时,该LNA的功耗为12.5mW,面积为1.1mm×0.9 mm.使用新颖的静电防护(ESD)结构使得在外围PAD上的保护二极管面积仅为8 μm×8 μm时,静电防护能力可达2 kV(人体模型)     

Monolithically integrated long wavelength photoreceiver OEIC based on InP/InGaAs HBT technology

The epitaxial structure and growth, circuit design, fabrication process and characterization are described for the photoreceiver opto-electronic integrated circuit (OEIC) based on the InP/lnGaAs HBT/PIN photodetector integration scheme. A 1.55 μm wavelength monolithically integrated photoreceiver OEIC is demonstrated with self-aligned InP/lnGaAs heterojunction bipolar transistor (HBT) process. The InP/lnGaAs HBT with a 2 μm × 8 μm emitter showed a DC gain of 40, a DC gain cutoff frequency of 45 GHz and a maximum frequency of oscillation of 54 GHz. The integrated InGaAs photodetector exhibited a responsivity of 0.45 AAV at λ = 1.55 μm, a dark current less than 10 nA at a bias of -5 V and a -3 dB bandwidth of 10.6 GHz. Clear and opening eye diagrams were obtained for an NRZ 223-l pseudorandom code at both 2.5 and 3.0 Gbit/s. The sensitivity for a bit error ratio of 10-9 at 2.5 Gbit/s is less than -15.2 dBm.     

High frequency characteristics of InAs/GaInAs quantum dotdistributed feedback lasers emitting at 1.3 μm

The high frequency properties of InAs/GaInAs quantum dot distributed feedback (DFB) lasers emitting at 1.3 μm have been examined. The lasers display a small static linewidth of 1.3 MHz and a chirp as low as 83 MHz/mA. More than 5 GHz small-signal modulation bandwidth was observed in the first devices indicating the potential for high-speed operation of quantum dot lasers     

A CMOS Direct Injection-Locked Frequency Divider With High Division Ratios

A CMOS injection-locked frequency divider (ILFD) with high division ratios and high frequency operation is presented. It consists of a ring oscillator and injection capacitors. An input signal is directly injected through the capacitors into the feedback nodes of the ring oscillator. The proposed ILFD is fabricated in a $0.18~mu{rm m}$ CMOS process and has a chip core size of $68~mu{rm m}times 70~mu{rm m}$. It shows multiple division ratios of 3, 6, and 9. The operation frequency is from 2.2 to 30.95 GHz. At the maximum operation frequency, the ILFD has a locking range of 260 MHz with an input power of less than 0.25 dBm, a division ratio of 9, and a power consumption of 12.5 mW. The locking range increases up to 3.2 GHz as the division ratio and the operation frequency decrease.