基于翻转信息熵的组合逻辑电路功耗分析

基于信息熵的复杂度分析方法是在VLSI设计流程的高层次抽象阶段对组合逻辑电路功耗和面积进行分析估计的可行方法之一.本文通过提出新的利用翻转信息熵进行电路实现面积和功耗估计的理论方法,改善了面积和功耗估计精度.大量基于随机电路和BENCHMARK电路的实验结果表明,上述方法能够使面积和功耗估计的相对误差分别降低24.3% (从12.74%到9.65%)和15.4% (从13.67%到11.57%).     

用遗传算法实现CMOS时序电路最大功耗估计

最大功耗分析对于设计高可靠性的VLSI芯片是非常重要的。实际中,总是在有限的计算时间内获取一个近似最大功耗。文中用遗传算法来选择具有高功耗的输入及内部状态模型,对电路进行仿真,实现时序电路的最大功耗估算;同时,实现了基于统计的逻辑模拟最大功耗估计方法。基于ISCAS89基准时序电路的仿真表明,新方法在大规模门数时具有明显的优势,估算精度较高。而且新方法的计算时间基本上是电路逻辑门的线性关系。     

冒险共振现象及其在CMOS电路最大功耗估计中的应用

随着集成电路工艺的不断提高，CMOS电路规模不断增大，功耗成为集成电路设计主要指标之一。文章首先以多位比较器为例，阐述了存在于部分多位电路功能块中的冒险共振现象；然后给出其在VLSI电路最大功耗估计中的应用。ISCAS85电路集实验结果证实了文章思路的有效性。     

一种基于相关系数的频率估计算法

针对单点频信号,基于相关系数,在现有频率估计方法的基础上,提出了一种新的频率估计算法,称之为相关测频算法。该方法在FFT的基础上,结合相关系数进行估计。理论研究和仿真分析表明:当被估计信号的信噪比较大时,相关测频算法的估计误差接近Cramer-Rao下界。与迭代插值FFT估计算法和改进Rife算法相比,相关测频算法的估计精度略低,但计算量较低,适合工程应用。     

VLSI低功耗技术研究

功耗已成为超大规模集成电路所面临的最大技术挑战之一.这就需要在不断满足设计要求的同时,不断提出新的方法来降低功耗.文章首先概述了VLSI的功耗问题,进而提出了VLSI功耗的来源,最后提出了降低CMOS集成电路功耗的技术与方法.     

一种单芯片DVB-C解调器的VLSI实现

设计了一个单芯片实现的用于DVB-C的QAM解调器.片上集成有3.3V 10位精度的40MSPS模数转换器及FEC前向纠错解码器.该芯片支持4～256QAM多种模式,最高码率达80Mbps,具有宽的载波频偏捕获范围.采用改进的算法及VLSI实现结构,性能稳定,面积优化.采用SMIC 0.25μm 1P5M混合信号CMOS工艺制造,面积为3.5mm×3.5mm,最大功耗为447mW.     

一种单芯片DVB-C解调器的VLSI实现

设计了一个单芯片实现的用于DVB-C的QAM解调器．片上集成有3.3V 10位精度的40MSPS模数转换器及FEC前向纠错解码器．该芯片支持4～256QAM多种模式，最高码率达80Mbps，具有宽的载波频偏捕获范围．采用改进的算法及VLSI实现结构，性能稳定，面积优化．采用SMIC 0.25μm 1P5M混合信号CMOS工艺制造，面积为3.5mm×3.5mm，最大功耗为447mW．     

测试向量中未确定位对测试功耗优化的影响

文章通过调整测试向量未确定位的数目，来考虑测试向量中未确定位对测试功耗优化的影响。ISCAS85和ISCAS89电路集的实验结果表明：无论对于组合电路还是时序电路，随着测试向量中未确定位数目的增加，未优化测试功耗有明显的降低，同时对于本文所考察的三种测试功耗优化方法，它们的优化效果均有明显的改善，其中海明距离优化方法的优化效果改善最大，当未确定位数目增加到90％以上时，可以用海明距离优化方法替代另外两种耗时的优化方法，直接到CMOS VLSI时序电路测试功耗进行优化。     

综合孔径辐射计中幅度误差校正方法研究

提出了一种校正1bit量化综合孔径辐射计中幅度误差的方法,这种方法直接通过测量噪声注入时1bit相关器的输出值来实时估计接收机噪声温度,进而校正由于不相关接收机噪声导致通道间信号相关系数的幅度下降,避免了传统方法中功率测量单元(PMS)的使用,降低了系统复杂度.分析表明,该方法的校正精度与功率测量单元校正的精度相当.     

CMOSVLSI电路最大功耗估计

最大功耗分析对于设计高可靠性的VLSI芯片是非常重要的.由于电路功耗强依赖于其输入模式,对有大量管脚的CMOS组合或时序电路,不能采用穷举搜索.本文用遗传算法来选择具有高功耗的输入及内部状态模型,在逻辑仿真基础上实现CMOS电路的最大功耗估算.同时用逻辑仿真的统计方法来衡量获得最大功耗的质量.基于ISCAS85和ISCAS89基准电路的仿真表明,新方法在大规模门数时具有明显的优势,估算精度较高.而且新方法的计算时间基本上是电路逻辑门的线性关系.     

TFT-LCD驱动控制电路芯片研究

研制成功一款彩屏手机用262144色132RGB×176-dot分辨率TFT-LCD单片集成驱动控制电路芯片,提出了基于低/中/高混合电压工艺、数模混合信号VLSI显示驱动芯片的设计及其验证方法,开发了SRAM访问时序冲突解决电路、二级输出驱动电路和动态负载补偿输出缓冲电路等新型电路结构,有效减小了电路的功耗和面积,抑制了回馈电压的影响,提高了液晶显示画面质量。采用0.25μm混合电压CMOS工艺实现的工程样片一次性流片成功,整个芯片的静态功耗约为5mW,输出灰度电压的安定时间小于30μs,芯片性能指标均达到设计要求。     

26万色TFT-LCD单片集成驱动芯片的Top-Down设计

提出了应用于TFT-LCD单片集成驱动芯片的Top-down设计技术,并成功开发了一款26万色、176RGB×220分辨率的TFT-LCD驱动芯片.该芯片是典型的混合信号超大规模集成电路芯片,采用0.18μm HV CMOS工艺制造.在26万色显示模式下,芯片的静态功耗是5mW,输出驱动电压的建立时间(0.2%误差范围内)小于26pμs.     

Low-power encodings for global communication in CMOS VLSI

Technology trends and especially portable applications are adding a third dimension (power) to the previously two-dimensional (speed, area) VLSI design space. A large portion of power dissipation in high performance CMOS VLSI is due to the inherent difficulties in global communication at high rates and we propose several approaches to address the problem. These techniques can be generalized at different levels in the design process. Global communication typically involves driving large capacitive loads which inherently require significant power. However, by carefully choosing the data representation, or encoding, of these signals, the average and peak power dissipation can be minimized. Redundancy can be added in space (number of bus lines), time (number of cycles) and voltage (number of distinct amplitude levels). The proposed codes can be used on a class of terminated off-chip board-level buses with level signaling, or on tristate on-chip buses with level or transition signaling     

Bus-invert coding for low-power I/O

Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period). For CMOS circuits most power is dissipated as dynamic power for charging and discharging node capacitances. This is why many promising results in low-power design are obtained by minimizing the number of transitions inside the CMOS circuit. While it is generally accepted that because of the large capacitances involved much of the power dissipated by an IC is at the I/O little has been specifically done for decreasing the I/O power dissipation. We propose the bus-invert method of coding the I/O which lowers the bus activity and thus decreases the I/O peak power dissipation by 50% and the I/O average power dissipation by up to 25%. The method is general but applies best for dealing with buses. This is fortunate because buses are indeed most likely to have very large capacitances associated with them and consequently dissipate a lot of power     

A multi coding technique to reduce transition activity in VLSI circuits

Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.     

多媒体SOC芯片的低功耗设计

从集成电路功耗原理出发,分析了CMOS电路功耗的来源,从集成电路设计的系统级、算法级、架构级、电路/门级以及工艺/器件级五个抽象层次出发,整理、总结了当前主要的低功耗设计方法,并在实际的移动多媒体处理应用SOC芯片设计中,平衡产品成本、设计复杂度、设计环境等多种因素,确定并应用了适合设计对象的低功耗设计方法的组合.通过对于样片功耗的测试分析,低功耗设计方法(组合)取得了预期的效果,实现了较低的动态功耗与很低的静态功耗.     

Power dissipation of VLSI array processing systems

The Power Factor Approximation (PFA) power estimation method is reviewed and applied to VLSI array processing systems. The power dissipation of 1, 2, and 3 dimensional algorithms implemented on linear, hexagonal, and cubic processor arrays is investigated. Closed form equations are developed which show how the overall power dissipation is influenced by an algorithm's size and dimensionality, the target array processor's size and dimensionality, and the adopted partitioning strategy. The power estimation methods developed in this paper can be applied in the early phases of VLSI algorithm/architecture design, selection, and partitionment. The power dissipation of a matrix-matrix multiplication operation is estimated as an example application.This work was supported in part by the Hughes Aircraft Company fellowship program and the NSF initiation grant MIP-99-10437.     

A Low-Power Digital IC Design Inside the Wireless Endoscopic Capsule

This paper proposes an architecture of the wireless endoscopy system for the diagnoses of whole human digestive tract and real-time endoscopic image monitoring. The low-power digital IC design inside the wireless endoscopic capsule is discussed in detail. A very large scale integration (VLSI) architecture of three-stage clock management is applied, which can save 46% power inside the capsule compared with the design without such a low-power design. A stoppable ring crystal oscillator with minimal overhead is used in the sleep mode, which results in about 60-muW system power dissipation in sleep mode. A new image compression algorithm based on Bayer image format and its corresponding VLSI architecture are both proposed for low-power, high-data volume. Thus, 8 frames per second with 320*288 pixels can be transmitted with 2 Mb/s. The digital IC design also assures that the capsule has many flexible and useful functions for clinical application. The digital circuits were verified on field-programmable gate arrays and have been implemented in 0.18-mum CMOS process with 6.2 mW     

航空电子设备故障诊断技术研究综述

随着电子技术的发展,电子设备组成的复杂化和智能化不断提高,IC芯片制造工艺的不断提高使得VLSI电路的集成密度增加,亦加大了电路故障测试的复杂性和困难度。本文综述了电子电路的通用测试方法和技术,并分析了局限性。详细叙述了刚刚发展起来的基于知识的故障诊断方法,它的应用使对于一个较复杂的电子设备进行准确故障诊断成为可能,并对其发展进行了探讨和展望。