功率MOSFET器件SEGR敏感区域的模拟研究

单粒子栅极穿通（SEGR）是功率MOSFET器件在空间应用时非常重要的失效模式。功率MOSFET的元胞区被普遍认为是对SEGR最敏感的区域。然而试验结果表明SEGR可能会发生在栅极的走线区域,而不是元胞区域。本文通过仿真软件对功率MOSFET内部的三种结构进行模拟评估,发现如果满足某些条件,元胞区域以外的区域可能成为SEGR的敏感区域。最后,对于不同区域本为给出了抑制SEGR的建议。     

SEGR- and SEB-hardened structure with DSPSOI in power MOSFETs

Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application.Single event gate rupture (SEGR) and single event burnout (SEB),which will degrade the running safety and reliability of spacecraft,are the two typical failure modes in power MOSFETs.In this paper,based on recombination mechanism of interface between oxide and silicon,a novel hardened power MOSFETs structure for SEGR and SEB is proposed.The structure comprises double stagger partial silicon-on-insulator (DSPSOI) layers.Results show that the safety operation area (SOA) of a 130 V N-channel power MOSFET in single event irradiation environment is enhanced by up to 50％ when the linear-energy-transfer value of heavy ion is a constant of 98 MeV.cm2/mg in the whole incident track,and the other parameters are almost maintained at the same value.Thus this novel structure can be widely used in designing single event irradiation-hardened power MOSFETs.     

Intrinsic threshold voltage fluctuations in decanano MOSFETs due tolocal oxide thickness variations

Intrinsic threshold voltage fluctuations introduced by local oxide thickness variations (OTVs) in deep submicrometer (decanano) MOSFETs are studied using three-dimensional (3-D) numerical simulations on a statistical scale. Quantum mechanical effects are included in the simulations employing the density gradient (DG) formalism. The random Si/SiO₂ and gate/SiO₂ interfaces are generated from a power spectrum corresponding to the autocorrelation function of the interface roughness. The impact on the intrinsic threshold voltage fluctuations of both the parameters used to reconstruct the random interface and the MOSFET design parameters are studied using carefully designed simulation experiments. The simulations show that intrinsic threshold voltage fluctuations induced by local OTV become significant when the dimensions of the devices become comparable to the correlation length of the interface. In MOSFETs with characteristic dimensions below 30 nm and conventional architecture, they are comparable to the threshold voltage fluctuations introduced by random discrete dopants     

功率VDMOS器件的SEB致SEGR效应研究

功率VDMOS器件是航天器电源系统配套的核心元器件之一,在重粒子辐射下会发生单粒子烧毁(SEB)和单粒子栅穿(SEGR)效应,严重影响航天器的在轨安全运行。本文在深入分析其单粒子损伤机制及微观过程的基础上,发现了功率VDMOS器件在重粒子辐射下存在SEBIGR效应,并在TCAD软件和¹⁸¹Ta粒子辐射试验中进行了验证。引起该效应的物理机制是,重粒子触发寄生三极管,产生瞬时大电流,使得硅晶格温度升高,高温引起栅介质层本征击穿电压降低,继而触发SEGR效应。SEBIGR效应的发现为深入分析功率MOSFET器件的单粒子辐射效应奠定了理论基础。     

Low-voltage hot-electron currents and degradation indeep-submicrometer MOSFETs

Hot-electron currents and degradation in deep submicrometer MOSFETs at 3.3 V and below are studied. Using a device with L _eff=0.15 μm and T_ox=7.5 nm, substrate current is measured at a drain bias as low as 0.7 V; gate current is measured at a drain bias as low as 1.75 V. Using the charge-pumping technique, hot-electron degradation is also observed at drain biases as low as 1.8 V. These voltages are believed to be the lowest reported values for which hot-electron currents and degradation have been directly observed. These low-voltage hot-electron phenomena exhibit similar behavior to hot-electron effects present at higher biases and longer channel lengths. No critical voltage for hot-electron effects (such as the Si-SiO₂ barrier height) is apparent. Established hot-electron degradation concepts and models are shown to be applicable in the low-voltage deep submicrometer regime. Using these established models, the maximum allowable power supply voltage to insure a 10-year device lifetime is determined as a function of channel length (down to 0.15 μm) and oxide thicknesses     

Counter doping into uniformly and heavily doped channel region ofsub-0.1 μm SOI MOSFETs

We proposed counter doping into a heavily and uniformly doped channel region of SOI MOSFETs. This enabled us to suppress the short channel effects with proper threshold voltage V_th and to eliminate parasitic edge or back gate transistors. We derived a model for V_th as a function of the projected range, Rp and dose, Φ_D, of the counter doping, and showed that V_th is invariable even when the as-implanted counter doping profile redistributes. Using this technology, we demonstrated a V_th roll-off free 0.075 μm-L_Geff nMOSFET with low off-state current     

An explicit expression for surface potential at high-end ofmoderate inversion

There is a moderate inversion region between the weak and strong inversion regions of MOSFET operation. This region is very important for designing analog circuits. This paper presents a new explicit expression for the surface potential at the high-end of the moderate inversion, which is useful for a circuit modeling. This expression allows a new definition for the threshold voltage V_th and a model of the relation between off-current I_off and on-current I_on of MOSFETs. A source resistance R_s has large influence on I_on, so that a model for R_s was newly developed. Proposed models for V_th and I_off-I_on characteristics were compared with experiments. It is found that the new definition Of Vth could apply to both short- and long-channel MOSFETs. The model revealed different I_off-I_on behaviors between high and low halo dose MOSFETs     

Current-crowding effect in diagonal MOSFET's

Electrical and reliability characteristics of diagonally shaped n-channel MOSFETs have been extensively investigated. Compared with the conventional device structure, diagonal MOSFETs show longer device lifetime under peak I_sub condition (V_g =0.5 V_d). However, in the high-gate-bias region (V_g=V_d), diagonal MOSFETs exhibit a significantly higher degradation rate. From the I_sub versus gate voltage characteristics, this larger degradation rate under high gate bias is concluded to be due mainly to the current-crowding effect at the drain corner. For a cell-transistor operating condition (V_g>V_d), this current-crowding effect in the diagonal transistor can be a serious reliability concern     

Off-state gate current in n-channel MOSFETs with nitrided oxidegate dielectrics

The authors report on the off-state gate current (I_g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I_g at drain voltages as low as 4 V and an I_g injection efficiency reaching 0.8, as compared to 8.5 V and 10^-7 in SiO₂ devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I_g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure     

Low-temperature processed MOSFETs with liquid phase deposited SiO2-xFx as gate insulator

Device performances of MOSFETs with SiO_2-xF_x gate oxides prepared by an extremely low-temperature (15°C) liquid phase deposition (LPD) method were investigated. The electrical characteristics, including threshold voltage of 2.1 V, peak effective mobility (μ_eff) of 525 cm²/V·s, and subthreshold swing of 134 mV/decade, show the devices exhibit comparable performance to other low-temperature processed MOSFETs. This demonstrates that LPD SiO_2-xF_x can be a suitable candidate for future gate insulators in low-temperature processed MOSFETs     

Process integration and device performance of a submicrometerBiCMOS with 16-GHz ft double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n⁺ buried layer, and n-channel MOSFETs were built in a p-well on a p⁺ buried layer. Deep trenches with depths of 4 μm and widths of 1 μm isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C_L=0 pF and 300 ps for C_L=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 μm were maintained at almost the same ratio     

An 1800 V triple implanted vertical 6H-SiC MOSFET

6H silicon carbide vertical power MOSFETs with a blocking voltage of 1800 V have been fabricated. Applying a novel processing scheme, n ⁺ source regions, p-base regions and p-wells have been fabricated by three different ion implantation steps. Our SiC triple ion implanted MOSFETs have a lateral channel and a planar polysilicon gate electrode. The 1800 V blocking voltage of the devices is due to the avalanche breakdown of the reverse diode. The reverse current density is well below 200 μA/cm² for drain source voltages up to 90% of the breakdown voltage. The MOSFETs are normally off showing a threshold voltage of 2.7 V. The active area of 0.48 mm² delivers a forward drain current of 0.3 A at Y_GS=10 V and V _DS=8 V. The specific on resistance was determined to 82 mΩdcm² at 50 mV drain source voltage and at V_GS =10 V which corresponds to an uppermost acceptable oxide field strength of about 2.7 MV/cm. This specific on resistance is an order of magnitude lower than silicon DMOSFET's of the same blocking capability could offer     

Suppression of boron penetration in p-channel MOSFETs usingpolycrystalline Si1-x-yGexCy gatelayers

Boron penetration through thin gate oxides in p-channel MOSFETs with heavily boron-doped gates causes undesirable positive threshold voltage shifts. P-channel MOSFETs with polycrystalline Si_1-x-yGe_xC_y gate layers at the gate-oxide interface show substantially reduced boron penetration and increased threshold voltage stability compared to devices with all poly Si gates or with poly Si_1-xGe gate layers. Boron accumulates in the poly Si_1-x-yGe_xC_y layers in the gate, with less boron entering the gate oxide and substrate. The boron in the poly Si_1-x-yGe_xC_y appears to be electrically active, providing similar device performance compared to the poly Si or poly Si_1-xGe_x gated devices     

A new DC Drain-Current-Conductance method (DCCM) for thecharacterization of effective mobility (μeff) and seriesresistances (Rs, Rd) of fresh and hot-carrierstressed graded junction MOSFETs

A simple new DC technique is developed to extract the gate bias dependent effective channel mobility (u_eff) and series resistances (R_s and R_d) of graded junction n- and p-channel MOSFETs. This technique is found to be accurate and effective for devices with differing channel lengths and also for devices after nonuniform hot-carrier degradation. The parameter values extracted provide further insight into the damage mechanisms of hot-carrier stressed graded junction nMOSFETs and are usable in circuit and reliability simulation. This technique is especially useful for the optimization of hot-carrier resistant structures of submicrometer MOSFETs     

Substrate bias dependence of subthreshold slopes in fully depletedsilicon-on-insulator MOSFET's

Subthreshold slopes in submicrometer n-channel MOSFETs in depleted silicon-on-insulator (SOI) films were measured as a function of substrate bias and temperature, as well as drain bias. It is found that for low drain voltage, a simple capacitor model can explain the result. For large drain voltages, anomalously sharp threshold slopes are observed for very negative substrate biases, but the anomalous effects are greatly reduced with a more positive substrate bias. A qualitative model based on the charge state of the lower SOI interface is proposed to explain the dependence of the anomalous effects on substrate bias     

Analytical modeling of the two-dimensional potential distribution and threshold voltage of the SOI four-gate transistor

The two-dimensional (2-D) channel potential and threshold voltage of the silicon-on-insulator (SOI) four-gate transistor (G/sup 4/-FET) are modeled. The 2-D analytical body potential is derived by assuming a parabolic potential variation between the lateral junction-gates and by solving Poisson's equation. The model is used to obtain the surface threshold voltage of the G/sup 4/-FET as a function of the lateral gate bias and for all possible charge conditions at the back interface. The body-potential model is extendable to fully depleted SOI MOSFETs and can serve to depict the charge-sharing and drain-induced barrier-lowering effects in short-channel devices.     

A thermal activation view of low voltage impact ionization inMOSFETs

The authors present a thermal activation perspective for direct assessment of the low voltage impact ionization in deep-submicrometer MOSFETs. A comparison of the experimentally determined activation energy and a simple theoretical model is used to demonstrate the underlying mechanism responsible for impact ionization at low drain bias. The study indicates that the main driving force of impact ionization changes from the electric field to the lattice temperature with power-supply scaling below 1.2 V. This transition of driving force results in a linear relationship between log(I_SUB/I_D) and V_D at sub-bandgap drain bias, as predicted by the proposed thermally-assisted impact ionization model     

A Two-Dimensional Model for Interface Coupling in Triple-Gate Transistors

The influence of the fin width on substrate-to-gate coupling in long-channel silicon-on-insulator triple-gate transistors is investigated. A complementary analysis, taking into account both the "front coupling" (variation of the front-channel threshold voltage V_T1, as a function of the substrate bias V_G2) and "back coupling" (variation of the back-channel threshold voltage V_T2) as a function of the front-gate bias V_G1) characteristics has been carried out. It is shown that the back coupling, as opposed to the front coupling, is highly sensitive to the fin width in narrow-channel devices and can even be used in fin width extraction. Simple analytical 2-D models for the body potential, V_T1, and V_T2 have been developed to clarify the experimental data, showing in particular the gradual control of the back interface potential by the lateral gates in narrow fins. The model stands as a 2-D generalization of the Lim and Fossum's well-known 1-D interface coupling model     

A capacitance-based method for experimental determination ofmetallurgical channel length of submicron LDD MOSFETs

A capacitance based method for determining L_met the metallurgical channel length of MOSFET, is proposed in this paper. This method has been extensively evaluated via two-dimensional numerical device simulation of MOSFETs with different source/drain tip and channel impurity concentration profiles as well as different gate oxide thicknesses. For all the impurity profiles tested, results demonstrated that the accuracy in extracting L_met of MOSFETs with gate oxides thinner than 100 Å is better than 110 Å. This method is applicable even when there is significant source/drain reoxidation induced gate oxide thickening, as long as the gate oxide thickening is not extended into the region directly above the metallurgically defined channel region. Unlike the determination of L_eff, the effective electrical channel length, from the drain current, L_met is extracted from capacitance data and the extraction is free from complications that can be introduced by incomplete removal of the resistive effects associated with contacts and the lightly doped source/drain region. Extensive measurements were performed on MOSFETs of different technologies. It is shown that the measurement is accurately repeatable and no device stressing is experienced over the required bias range. The L_met and L_eff extracted from measured capacitance and drain current data are compared. Results showed that L _met is typically 700 to 1200 Å shorter for submicron MOS technologies, but it tracks with L_eff, i.e. a shorter L _met corresponds to a shorter L_eff     

New channel engineering for sub-100 nm MOS devices considering bothcarrier velocity overshoot and statistical performance fluctuations

We introduce a new channel engineering design for nano-region SOI and bulk MOSFETs taking into account both carrier velocity overshoot and statistical performance fluctuations. For types of both device, in the high gate drive region, the high field carrier velocity υ_e is not degraded at channel dopant density N_a lower than 1×10¹⁷ cm^-3, according to an experimental universal relationship between υ_e and the low field mobility. On the other hand, there is a most suitable N_a condition for suppression of statistical threshold voltage fluctuations. This most suitable N_a is slightly higher for SOI devices than that for bulk MOSFETs, but it is lower than 1×10 ¹⁷ cm^-3 in both cases. Therefore, this most suitable N_a condition is consistent with the above N_a condition for carrier velocity. Consequently, new N_a conditions for nano region devices are introduced in this study. N_a should be designed to be of the order of 1×10¹⁶ cm^-3 rather than rising by the usual scaling rule, but it is necessary to suppress the short channel effects of SOI and bulk MOSFETs by scaling down the SOI thickness, and to use source/drain junction depth scaling or surface low impurity structures in bulk MOSFETs, respectively