Low-cost test technique using a new RF BIST circuit for 4.5-5.5 GHz low noise amplifiers

This paper presents a low-cost test technique using a new RF Built-In Self-Test (BIST) circuit for 4.5-5.5 GHz low noise amplifiers (LNAs). The test technique measures input impedance, voltage gain, noise figure, input return loss and output signal-to-noise ratio of the LNA. The BIST circuit is designed using 0.18 μm SiGe technology. The BIST circuit contains test amplifier and RF peak detectors. The complete measurement set-up contains LNA with BIST circuit, external RF source, RF relays, 50 Ω load impedance, and a DC voltmeter. The test technique utilizes output DC voltage measurements and these measured values are translated to the LNA specifications such as input impedance and gain through the developed equations. The technique is simple and inexpensive.     

A New Automatic Compensation Network for System‐on‐Chip Transceivers

This paper proposes a new automatic compensation network (ACN) for a system‐on‐chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on‐chip ACN using 0.18 µm SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design‐for‐testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.     

Low-Cost Testing of 5 GHz Low Noise Amplifiers Using New RF BIST Circuit

This paper presents a new low-cost RF BIST (Built-In Self-Test) scheme that is capable of measuring input impedance, gain, noise figure and input return loss for a low noise amplifier (LNA) in RF systems. The RF BIST technique requires an additional RF amplifier and two peak detectors, and its output is a DC voltage level. The BIST circuit is designed using 0.18 μm SiGe technology. The test technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the developed mathematical equations. Simulation results are presented for an LNA working at 5 GHz. Measurement data are compared with simulation results to validate the developed mathematical equations. The technique is simple and inexpensive. Jee-Youl Ryu received the BS and MS degrees in 1993 and 1997 from Pukyong National University in Electronic Engineering, Pusan, South Korea respectively. He also received the PhD degree in 2004 from Arizona State University in Electrical Engineering, Arizona, USA. He is currently with Samsung SDI Co., Ltd. His current research interests include RF IC design and testing, MMIC design and testing, analog IC design and testing, passives modeling, testing and analysis, and MEMS technology. Dr. Bruce Kim received the B.S.E.E. degree from the University of California, Irvine in 1981, the M.S. degree in electrical engineering from the University of Arizona in 1985, and the Ph.D. degree in electrical engineering from Georgia Institute of Technology in 1996. He was an Associate Professor at Arizona State University until 2005. Currently, he is an Associate Professor at The University of Alabama. His current research interests include RF IC testing, MEMS integration and VLSI circuits. He has been working on SiP testing technologies, package electrical modeling, and measurements of RF IC packages. Dr. Kim is a 1997 recipient of the National Science Foundation's CAREER Award and received the Meritorious Award from IEEE. He serves as the Chair of the IEEE CPMT Society TC-Electrical Test, associate editor of the IEEE Transactions on Advanced Packaging, associate editor of Design and Test of Computers, and program committee member of Electronic Components and Technology Conference. He is a senior member of IEEE.     

A Novel RF Test Scheme Based on a DFT Method

This paper presents a new RF testing scheme based on a design-for-testability (DFT) method for measuring functional specifications of RF integrated circuits (IC). The proposed method provides the input impedance, gain, noise figure, voltage standing wave ratio (VSWR) and output signal-to-noise ratio (SNR) of a low noise amplifier (LNA). The RF test scheme is based on theoretical expressions that produce the actual RF device specifications by utilizing the output DC voltages from the DFT chip. This technique can save marginally failing chips in production testing as well as in the system, hence saving a tremendous amount of revenue from unnecessary device replacements.     

一种用于GPS接收机的低噪声放大器

针对GPS接收机低功耗、低噪声、高增益的要求,采用功率限制下噪声匹配技术、阻抗匹配技术和电源复用技术,设计了一款可应用于GPS接收机的单端输入差分输出低噪声放大器,减少了巴伦损耗。采用SMIC 0.13 SymbolmAm CMOS RF工艺和全定制集成电路设计方法,工作频率为1575 GHz,对电路进行版图后仿真。仿真结果表明,该低噪声放大器在1.2 V电源电压下,功耗为4.8 mW,增益为22.65 dB,噪声系数为1.388 dB。     

Optimization of input impedance and mechanism of noise suppressionin a DC SQUID RF amplifier

The optimal input impedance and noise of a DC SQUID RF amplifier at frequencies of the order of 1 GHz with a resonant input matching circuit have been studied analytically, numerically, and experimentally. A model for noise temperature and power gain has been developed for the practical resonant input tank circuit. A new effect of the output noise increasing or decreasing with changing the sign of voltage-to-flux transfer coefficient has been observed experimentally and explained analytically. The different values of noise temperature for the opposite dV/dΦ values have been interpreted using a model with partially correlated current and voltage noise sources. The equivalent layout for optimal input matching of a SQUID amplifier comprising series and parallel resonant circuits has been presented. Using such a matching circuit and SIS junction as a signal source the SQUID amplifier noise temperature about 1 K has been measured at 1.1 GHz     

W‐Band MMIC chipset in 0.1‐μm mHEMT technology

We developed a 0.1‐μm metamorphic high electron mobility transistor and fabricated a W‐band monolithic microwave integrated circuit chipset with our in‐house technology to verify the performance and usability of the developed technology. The DC characteristics were a drain current density of 747 mA/mm and a maximum transconductance of 1.354 S/mm; the RF characteristics were a cutoff frequency of 210 GHz and a maximum oscillation frequency of 252 GHz. A frequency multiplier was developed to increase the frequency of the input signal. The fabricated multiplier showed high output values (more than 0 dBm) in the 94 GHz–108 GHz band and achieved excellent spurious suppression. A low‐noise amplifier (LNA) with a four‐stage single‐ended architecture using a common‐source stage was also developed. This LNA achieved a gain of 20 dB in a band between 83 GHz and 110 GHz and a noise figure lower than 3.8 dB with a frequency of 94 GHz. A W‐band image‐rejection mixer (IRM) with an external off‐chip coupler was also designed. The IRM provided a conversion gain of 13 dB–17 dB for RF frequencies of 80 GHz–110 GHz and image‐rejection ratios of 17 dB–19 dB for RF frequencies of 93 GHz–100 GHz.     

Fault Coverage Analysis of Peak-Detector Based BIST for RF LNAs

Analog and mixed-signal testing is becoming an important issue that affects both the time-to-market and the product cost of many SoCs. In order to provide an efficient testing method for 865–870 MHz low noise amplifiers (LNAs), which constitute a mixed-signal circuit, a novel BIST method is developed. This BIST can be easily implemented with a RF peak detector and two comparators. The circuit used in the test and the LNA are designed using 0.35 μm CMOS technology. The simulation results show higher fault coverage than that of previous test methods. A total of twenty eight short and open (catastrophic) faults and eleven variation parameters have been introduced into the LNA, giving fault coverage of 100% for catastrophic faults and parametric variation. Thus, it provides an efficient structural test, which is suitable for a production test in terms of an area overhead, a test accessibility, and test time.     

433MHz ASK接收机射频前端电路设计

设计了一款应用在433MHz ASK接收机中的射频前端电路。在考虑了封装以及ESD保护电路的寄生效应的同时,从噪声、匹配、增益和线性度等方面详细讨论了低噪声放大器和下混频器的电路设计。采用0.18μm CMOS工艺,在1.8V的电源电压下射频前端电路消耗电流10.09 mA。主要的测试结果如下:低噪声放大器的噪声系数、增益、输入P1dB压缩点分别为1.35 dB、17.43 dB、-8.90dBm;下混频器的噪声系数、电压增益、输入P1dB压缩点分别为7.57dB、10.35dB、-4.83dBm。     

Self-Calibration of Output Match and Reverse Isolation in LNAs Based Switchable Resistor

With recent advances in CMOS process technology, the concept of system-on-a-chip (SoC) has been realized by integrating more and more digital and analog building blocks in a single chip [2, 9]. Additionally, these advances have brought several new types of processes faults (soft fault) and higher process variations to RF circuit resulting performances degradation. In order to compensate the RF circuit performance, a novel efficient self-calibration method for 865?C870?MHz low noise amplifiers (LNAs), which constitute a RF mixed-signal circuit, is developed. This technique detects any deviation from the output match and from reverse isolation using built-in self test (BIST) methods, and then provides a corrective measure to recalibrate these LNA performances to the possible optimal value. This proposed self-calibration technique uses a switchable resistor which has been designed to investigate its ability to compensate for output match S22 and reverse isolation S12 without affecting other LNA performances. The use of this method saves space on chip and prevents adding switch resistor noise. In addition, the new calibration design shows the ability to calibrate S22 and S12 due to the catastrophic fault.     

A switch‐controlled multimode narrowband receiver RF front‐end

This work illustrates a flexible and convenient method to build a multimode narrowband receiver RF front‐end by means of controlled switches, switched capacitors, and switched inductors. The front‐end comprises a dual‐gain‐mode narrowband low‐noise amplifier (LNA) and a dual‐linearity‐mode mixer. A four‐mode receiver RF front‐end constructed with the dual‐gain‐mode LNA and the dual‐linearity‐mode mixer operating in frequency band range from 1800 to 2050 MHz was demonstrated with an IBM 90‐nm CMOS process. The front‐end achieves a 1/1.6 dB noise figure, 30/20 dB power gain, and 16/?10 dBm third‐order input intercept point while draws a 5.9/3.6 mA current from a 1.8‐V supply voltage at the low noise mode and high linearity mode, respectively. The proposed technique can be employed to build an intelligent mobile system.     

A current based self-test methodology for RF front-end circuits

This paper presents a critical step in the realization of a robust, low overhead, current-based Built-In Self-Test (BIST) scheme for RF front-end circuits. The proposed approach involves sampling the high frequency supply current drawn by the circuit under test (CUT) and using it to extract information about various performance metrics of the RF CUT. The technique has inherently high fault coverage and can handle soft faults, hard faults as well as concurrent faults because it shifts the emphasis from detecting individual faults, to quantifying all the significant performance specifications of the CUT. This work also presents the realization of an HF current monitor which is a critical component in the proposed architecture. The current monitor has then been interfaced with three standard RF front-end circuits; a Low noise amplifier, a Single Balanced Mixer and a Voltage controlled oscillator, while minimally impacting their performance. The extracted information has then been used to create a mapping between variations in CUT performance and the sensed current spectrum. The monitor circuit has been fabricated in the IBM 6 metal, RF CMOS process, with a gain of 24 db and bandwidth of 3.9 GHz.     

A concurrent built-in self-test architecture based on a self-testing RAM

Manufacturing test is carried-out once to ensure the correct operation of the circuit under test right after fabrication, while testing is carried-out periodically to ensure that the circuit under test continues to operate correctly on the field. The use of offline built-in self-test (BIST) techniques for periodic testing imposes the interruption of the normal operation of the circuit under test. On the other hand, the use of input vector monitoring concurrent BIST techniques for periodic testing provides the capability to perform the test, while the circuit under test continues to operate normally. In this paper, a novel input-vector monitoring concurrent BIST technique for combinational circuits based on a self-testing RAM, termed R-CBIST, is presented. The presented technique compares favorably to the other input vector monitoring concurrent BIST techniques proposed so far with respect to the hardware overhead, and the time required for the concurrent test to be completed (concurrent test latency). R-CBIST can be utilized to test ROM because it results in small hardware overhead, whereas there is no need to stop the ROM normal operation.     

Design and optimization of CMOS LNA with ESD protection for 2.4 GHz WSN application

A new optimization method of a source inductive degenerated low noise amplifier(LNA) with electrostatic discharge protection is proposed.It can achieve power-constrained simultaneous noise and input matching. An analysis of the input impedance and the noise parameters is also given.Based on the developed method,a 2.4 GHz LNA for wireless sensor network application is designed and optimized using 0.18-μm RF CMOS technology. The measured results show that the LNA achieves a noise figure of 1.59 dB,a power gain of 14.12 dB, an input 1 dB compression point of-8 dBm and an input third-order intercept point of 1 dBm.The DC current is 4 mA under a supply of 1.8 V.     

A 900 MHz Zero‐IF RF Transceiver for IEEE 802.15.4g SUN OFDM Systems

This paper presents a 900 MHz zero‐IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ΔΣ fractional‐N frequency synthesizer. In the RF front end, re‐use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low‐noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current‐driven passive mixer in Rx and voltage‐mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty‐cycle in local oscillator clocks. The overall Rx‐baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a 0.18 μm CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of ?2 dBm, a sensitivity level of ?103 dBm at 100 Kbps with , an Rx input P_1dB of ?11 dBm, and an Rx input IP3 of ?2.3 dBm.     

An Efficient Built‐in Self‐Test Algorithm for Neighborhood Pattern‐ and Bit‐Line‐Sensitive Faults in High‐Density Memories

As the density of memories increases, unwanted interference between cells and the coupling noise between bit‐lines become significant, requiring parallel testing. Testing high‐density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built‐in self‐test (BIST) algorithm for neighborhood pattern‐sensitive faults (NPSFs) and new neighborhood bit‐line sensitive faults (NBLSFs). Instead of the conventional five‐cell and nine‐cell physical neighborhood layouts to test memory cells, a four‐cell layout is utilized. This four‐cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck‐at faults, transition faults, conventional pattern‐sensitive faults, and neighborhood bit‐line sensitive faults.     

Application of VSI‐EBG Structure to High‐Speed Differential Signals for Wideband Suppression of Common‐Mode Noise

In this paper, we present wideband common‐mode (CM) noise suppression using a vertical stepped impedance electromagnetic bandgap (VSI‐EBG) structure for high‐speed differential signals in multilayer printed circuit boards. This technique is an original design that enables us to apply the VSI‐EBG structure to differential signals without sacrificing the differential characteristics. In addition, the analytical dispersion equations for the bandgap prediction of the CM propagation in the VSI‐EBG structure are extracted, and the closed‐form expressions for the bandgap cutoff frequencies are derived. Based on the dispersion equations, the effects of the impedance ratio, the EBG patch length, and via inductances on the bandgap of the VSI‐EBG structure for differential signals are thoroughly examined. The proposed dispersion equations are verified through agreement with the full‐wave simulation results. It is experimentally demonstrated that the proposed VSI‐EBG structure for differential signaling suppresses the CM noise in the wideband frequency range without degrading the differential characteristics.     

Cost Effective Silica‐Based 100 G DP‐QPSK Coherent Receiver

We present a cost‐effective dual polarization quadrature phase‐shift coherent receiver module using a silica planar lightwave circuit (PLC) hybrid assembly. Two polarization beam splitters and two 90° optical hybrids are monolithically integrated in one silica PLC chip with an index contrast of 2%‐Δ. Two four‐channel spot‐size converter integrated waveguide‐photodetector (PD) arrays are bonded on PD carriers for transverse‐electric/transverse‐magnetic polarization, and butt‐coupled to a polished facet of the PLC using a simple chip‐to‐chip bonding method. Instead of a ceramic sub‐mount, a low‐cost printed circuit board is applied in the module. A stepped CuW block is used to dissipate the heat generated from trans‐impedance amplifiers and to vertically align RF transmission lines. The fabricated coherent receiver shows a 3‐dB bandwidth of 26 GHz and a common mode rejection ratio of 16 dB at 22 GHz for a local oscillator optical input. A bit error rate of is achieved at a 112‐Gbps back‐to‐back transmission with off‐line digital signal processing.     

A low power dual-band multi-mode RF front-end for GNSS applications

A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS,Bei-Dou,Galileo and Glonass systems is presented.It consists of a reconfigurable low noise amplifier(LNA),a broadband active balun,a high linearity mixer and a bandgap reference(BGR) circuit.The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail.By using two different LC networks at the input port and the switched cap...     

一个应用于卫星导航接收机的低功耗可配置双频多模射频前端

本文给出了一个应用于GPS、北斗、伽利略和Glonass四种卫星导航接收机的高性能双频多模射频前端。该射频前端主要包括有可配置的低噪声放大器、宽带有源单转双电路、高线性度的混频器和带隙基准电路。详细分析了寄生电容对源极电感负反馈低噪声放大器输入匹配的影响,通过在输入端使用两个不同的LC匹配网络和输出端使用开关电容的方法使低噪声放大器可以工作在1.2GHz和1.5GHz频带。同时使用混联的有源单转双电路在较大的带宽下仍能获得较好的平衡度。另外,混频器采用MGTR技术在低功耗的条件下来获得较高的线性度,并不恶化电路的其他性能。测试结果表明：在1227.6MHz和1557.42MHz频率下,噪声系数分别为2.1dB和2.0dB,增益分别为33.9dB和33.8dB,输入1dB压缩点分别0dBm和1dBm,在1.8V电源电压下功耗为16mW。