Design of Sub-1 mW CMOS LC VCO based on current reused topology with Q-enhancement and body-biased technique

A CMOS LC voltage controlled oscillator (VCO) based on current reused topology with low phase noise and low power consumption is presented for IEEE 802.11a (Seller et al. A 10 GHz distributed voltage controlled oscillator for WLAN application in a VLSI 65 nm CMOS process, in: IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 3–5 June, 2007, pp. 115–118.) application. The chip1 is designed with the tail current-shaping technique to obtain the phase noise −116.1 dBc/Hz and power consumption 3.71 mW at the operating frequency 5.2 GHz under supply voltage 1.4 V. The second chip of proposed VCO can achieve power consumption Sub 1 mW and is still able to maintain good phase noise. The current reused and body-biased architecture can reduce power consumption, and better phase noise performance is obtained through raising the Q value. The measurement result of the VCO oscillation frequency range is from 5.082 GHz to 5.958 GHz with tuning range of 15.8%. The measured phase noise is −115.88 dBc/Hz at 1 MHz offset at the operation frequency of 5.815 GHz. and the dc core current consumption is 0.71 mA at a supply voltage of 1.4 V. Its figure of merit (FOM) is −191 dBc/Hz. Two circuits were taped out by TSMC 0.18 μm 1P6M process.     

A 5-GHz low phase noise differential colpitts CMOS VCO

A low noise 5-GHz differential Colpitts CMOS voltage-controlled oscillator (VCO) is proposed in this letter. The Colpitts VCO core adopts only PMOS in a 0.18-/spl mu/m CMOS technology to achieve a better phase noise performance since PMOS has lower 1/f noise than NMOS. The VCO operates from 4.61 to 5 GHz with 8.3% tuning range. The measured phase noise at 1-MHz offset is -120.42 dBc/Hz at 5 GHz and -120.99 dBc/Hz at 4.61 GHz. The power consumption of the VCO core is only 3 mW. To the authors' knowledge, this differential Colpitts CMOS VCO achieves the best figure of merit (FOM) of 189.6 dB at 5-GHz band.     

Low-Phase Noise Hartley Differential CMOS Voltage Controlled Oscillator

This letter presents a novel Hartley low phase noise differential CMOS voltage-controlled oscillator (VCO). The low noise CMOS VCO has been implemented with the TSMC 0.18-mum 1P6M CMOS technology and adopts full PMOS to achieve a better phase noise performance. The VCO operates from 4.02 to 4.5GHz with 11.3% tuning range. The measured phase noise at 1-MHz offset is about -119dBc/Hz at 4.02GHz and 122dBc/Hz at 4.5GHz. The power consumption of the VCO core is 6.75mW     

单片CMOS UHF RFID阅读器中低噪声LC VCO的设计

设计了一种应用于单片CMOS超高频射频识别阅读器中的低功耗、低相位噪声LC VCO。根据超高频射频识别阅读器的系统架构和协议要求,对本振相位噪声要求做出详细讨论;采用LC滤波器和低压差调压器分别对尾电流源噪声和电源噪声进行抑制,提高了VCO相位噪声性能。电路采用IBM 0.18μm RF CMOS工艺实现,电源电压3.3 V时,偏置电流为4.5 mA,中心频率为1.8 GHz,在频偏1 MHz处,相位噪声为-136.25 dBc/Hz,调谐范围为30%。     

A low-phase-noise and low-power multiband CMOS voltage-controlled oscillator

A low voltage multiband all-pMOS VCO was fabricated in a 0.18-/spl mu/m CMOS process. By using a combination of inductor and capacitor switching, four band (2.4, 2.5, 4.7, and 5 GHz) operation was realized using a single VCO. The VCO with an 1-V power supply has phase noises at 1-MHz offset from a 4.7-GHz carrier of -126 dBc/Hz and -134 dBc/Hz from a 2.4-GHz carrier. The VCO consumes 4.6 mW at 2.4 and 2.5 GHz, and 6 mW at 4.7 and 5 GHz, respectively. At 4.7 GHz, the VCO also achieves -80 dBc/Hz phase noise at 10-kHz offset with 2 mW power consumption.     

Design of self-bias tail transistor technique for low phase noise CMOS VCO with harmonic suppression using capacitance ground

This paper presents a low phase noise wideband CMOS VCO based on the self-bias tail transistor technique and harmonic suppression using a capacitance ground. This VCO utilizes switching capacitor arrays in which four channels are able to be selected for multi-band application. Moreover, the design of CMOS VCO makes good use of the self-bias tail transistor and capacitance ground filter technique to reduce the phase noise. The MOS varactors are used as fine tuning for wideband operating application. The fully integrated VCO provides excellent performance with high FOM −193 dBc/Hz. The bandwidth of the frequency is 1.1 GHz and the tuning range is 13.8%. The power dissipation of the core circuit is 8.28 mW under a 1.8 V supply and phase noise is measured as low as −123.6 dBc/Hz at 1 MHz offset under 8.5 GHz oscillation frequencies. This VCO was made by the TSMC 0.18 μm 1P6M CMOS standard process and the chip area is 0.75×0.69 (mm²).     

A Low‐Spur CMOS PLL Using Differential Compensation Scheme

This paper proposes LC voltage‐controlled oscillator (VCO) phase‐locked loop (PLL) and ring‐VCO PLL topologies with low‐phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer‐resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out‐band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65‐nm or 45‐nm process. The measured results of the LC‐VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of –118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring‐VCO PLL shows a phase noise of –95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.     

Design and performance of a robust 180 nm CMOS standalone VCO and the integrated PLL

The design details of a low power/wide tuning range phase locked loop (PLL) is presented in 180 nm CMOS together with the simulated and post fabrication measured performance. The PLL has been specifically designed for applications requiring a wide tuning range (1.55–2.28 GHz) while maintaining low power consumption (18 mW) and good phase noise (−100.9 dBc/Hz at 1 MHz). The tuning range represents significant improvement over other reported PLL CMOS implementations. To illustrate the robustness of the architecture, a 90 nm CMOS design is included with a 5.8–9.45 GHz tuning range (48%), phase noise of −111.7 dBc/Hz, and power consumption of 18.6 mW. The stand alone voltage controlled oscillator (VCO) and the PLL were fabricated on a single 180 nm die providing a unique opportunity to analyze and measure both the stand alone VCO phase noise performance and the integrated PLL phase noise performance. The contributions to the PLL phase noise (phase detector, charge pump, VCO, divider, and reference source) are delineated and both the theoretical and measured PLL phase noise performance is discussed. Design tradeoffs are included such as effect of loop bandwidth on phase noise contributions.     

A 1-V 9.7-mW CMOS Frequency Synthesizer for IEEE 802.11a Transceivers

A 1-V CMOS frequency synthesizer is proposed for wireless local area network 802.11a transceivers using a novel transformer-feedback voltage-controlled oscillator (VCO) for low voltage and a stacked frequency divider for low power. Implemented in a 0.18-mum CMOS process and operated at 1-V supply, the VCO measures a phase noise of -140.5 dBc at an offset of 20 MHz with a center frequency of 4.26 GHz and a power consumption of 5.17 mW. Its tuning range is as wide as 920 MHz (23%). By integrating the VCO into a frequency synthesizer, a phase noise of -140.1 dBc/Hz at an offset of 20 MHz is measured at a center frequency of 4.26 GHz. Its output frequency can be changed from 4.112 to 4.352 GHz by switching the 3-bit modulus of the programmable divider. The synthesizer consumes only 9.7 mW and occupies a chip area of 1.28 mm².     

A fully integrated 5.8 GHz U-NII band 0.18-/spl mu/m CMOS VCO

A fully integrated 5.8 GHz CMOS L-C tank voltage-controlled oscillator (VCO) using a 0.18-/spl mu/m 1P6M standard CMOS process for 5 GHz U-NII band WLAN application is presented. The VCO core circuit uses only PMOS to pursue a better phase noise performance since it has less 1/f noise than NMOS. The measurement is performed by using a FR-4 PCB test fixture. The output frequency of the VCO is from 5860 to 6026 MHz with a 166 MHz tuning range and the phase noise is -96.9 dBc/Hz at 300 kHz (or -110 dBc/Hz at 1 MHz) with V ctrl = 0 V. The power consumption of the VCO excluding buffer amplifiers is 8.1 mW at V/sub DD/ = 1.8 V and the output power is -4 dBm.     

CMOS Colpitts Quadrature VCO Using the Body Injection-Locked Coupling Technique

This paper presents a new low phase noise quadrature voltage-controlled oscillator (QVCO), which consists of two differential complementary Colpitts voltage-controlled oscillators (VCOs) with a tail inductor. The output of the tail inductor in one differential VCO is injected to the bodies of the nMOSFETs in the other differential VCO and vice versa. The proposed CMOS QVCO has been implemented with the TSMC 0.18 mum CMOS technology and the die area is 0.725 times 0.839 mm². At the supply voltage of 1.1 V, the total power consumption is 9.9 mW. The free-running frequency of the QVCO is tunable from 5.26 GHz to 5.477 GHz as the tuning voltage is varied from 0.0 V to 1.1 V. The measured phase noise at 1 MHz frequency offset is -124.36 dBc/Hz at the oscillation frequency of 5.44 GHz and the figure of merit (FOM) of the proposed QVCO is -189.1 dBc/Hz.     

一种双带宽UHF主从耦合式LC VCO

为了满足无线通信系统应用需要,设计了一种主从耦合式LC压控振荡器(VCO).基于0.18 μm CMOS标准工艺,由一个5 GHz主VCO和两个起分频作用的从VCO组成,其中主VCO选用PMOS考毕兹差分振荡结构,在两个互补交叉耦合的从VCO的输出端之间设置有注入式NMOS器件以达到分频的目的.仿真及硬件电路实验结果表明,在1.8 V低电源电压下,5 GHz主VCO的调谐范围为4.68～5.76 GHz,2.5 GHz从VCO的调谐范围为2.32～2.84 GHz;在1 MHz的偏频下,5 GHz主VCO的相位噪声为118.2 dBc/Hz,2.5 GHz从VCO的相位噪声为124.4 dBc/Hz.另外,主从VCO的功耗分别为6.8 mW和7.9 mW,因此特别适用于低功耗、超高频短距离无线通信系统中.     

A 0.5 V LC-VCO with improved varactor tuning technique for WSN

A 0.5 V LC-VCO implemented in 0.18 μm CMOS technology for wireless sensor network is described in this paper. An improved varactor tuning technique is proposed to decrease low frequency noise up-conversion and AM–FM phase noise of VCO, also it can increase Q of LC tank and reduce power consumption of VCO. For coarse tuning of VCO, it can increase the varactor control voltage variation range. For fine tuning of VCO, it can reduce the varactor nonlinearity. The measured tuning range is 4.58–5.26 GHz and power consumption is 2.2 mW. The measured phase noise is ?114 dBc/Hz at 1 MHz frequency offset from a 4.8 GHz carrier.     

VCO Design With On-Chip Calibration System

This paper presents a low-supply voltage integrated CMOS voltage-controlled oscillator (VCO) with an on-chip digital VCO calibration control system. The VCO utilizes various state-of-the-art design methods to achieve low phase noise. The calibration system includes a novel high-speed digital divide by two circuit and a counter running on 1-GHz input to enable on-chip frequency measurement. An arithmetic unit and algorithms to perform the calibration are implemented using on-chip logic. Two different types of calibration methods have been implemented and measured in order to compare the proposed VCO gain optimization method with more conventional type of VCO calibration. The measurements show that the VCO design has phase noise from$-$120.5 dBc/Hz to$-$118.7 dBc/Hz @ 400-kHz offset, measured over the frequency range from 1.67 to 1.93 GHz. The proposed VCO gain optimization method is capable of reducing the$K_ VCO$peak-to-peak variation of the presented VCO design from 54.4% to 29.8% in DCS1800 and PCS1900 GSM transmission bands when compared to the conventional type of calibration method.     

A 1.0 V differential VCO in 0.13 μm CMOS technology

A differential complementary LC voltage controlled oscillator(VCO) with high Q on-chip inductor is presented.The parallel resonator of the VCO consists of inversion-mode MOS(I-MOS) capacitors and an on-chip inductor.The resonator Q factor is mainly limited by the on-chip inductor.It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz.The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process,and the chip area is 1.0×0.8 mm~2.The free-running frequency is from 5.73 to 6.35 GHz.When oscillating at 6.35 GHz,the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz.The figure of merit of the proposed VCO is -192.13 dBc/Hz.     

Dual-band ultra-wide tuning range CMOS voltage-controlled oscillator

A dual-band wide-tuning range LC CMOS voltage controlled oscillator (VCO) topology is proposed. Dual-band operation is realised by employing a double-tuned double-driven transformer as a resonator. The proposed approach eliminates MOS switches, which are typically used in multi-standard oscillators, and thus improves phase noise and tuning range characteristics. The concept is demonstrated through the design of an LC VCO in a standard 0.18 mum CMOS process. Two frequency bands are realised (2.4 and 6 GHz) with 740 MHz tuning range in the first band and 1.56 GHz tuning range in the second band. Operating from a 1.8 V supply, the VCO has a simulated phase noise of -119 dBc/Hz in the 2.4 GHz band and -110 dBc/Hz in the 6 GHz band at 600 KHz offset from the carrier     

基于90nmCMOS工艺的低功耗宽带压控振荡器设计

A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET(IMOS) varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27–32.5 GHz, exhibiting a frequency tuning range(FTR) of 18.4%and a phase noise of –101.38 d Bc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of –185d Bc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 m A DC current.     

Noise property of a quadrature balanced VCO

A quadrature balanced voltage controlled oscillator (B-VCO) with current source switching is proposed and analyzed. This letter shows analytically that the switching improves the phase noise. A switched transistor is also used as a coupling transistor to generate quadrature signals without degrading the phase noise. To investigate the effect of quadrature coupling on the phase noise, a single B-VCO and a quadrature B-VCO are implemented with identical components in an 0.18-/spl mu/m CMOS process. Both VCO cores draw about 8.8mA under a low bias voltage of 1.8V. The oscillation frequencies are 10.21GHz and 10.81GHz. The measured phase noises of the single at an offset frequency of 1MHz VCO is -114.83 dBc/Hz while that of the quadrature VCO is -116.67 dBc/Hz. The quadrature B-VCO is superior to the single B-VCO with respect to phase noise and oscillation frequency in the X-band.     

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a standard 0.5 /spl mu/m digital CMOS process for wireless communication. The voltage-controlled oscillator (VCO) required for the low-frequency loop is designed using a ring-type VCO and achieves a tuning range of 89% from 356 to 931 MHz and a phase noise of -109.2 dBc/Hz at 600 kHz offset from 856 MHz. With an active chip area of 2000/spl times/1000 /spl mu/m/sup 2/ and at a 2 V supply voltage, the whole synthesizer achieves a tuning range from 1.8492 to 1.8698 GHz in 200 kHz steps with a measured phase noise of -112 dBc/Hz at 600 kHz offset from 1.86 GHz. The measured settling time is 128 /spl mu/s and the total power consumption is 95 mW.     

A 98/196 GHz Low Phase Noise Voltage Controlled Oscillator With a Mode Selector Using a 90 nm CMOS Process

A 98/196 GHz low phase noise voltage controlled oscillator (VCO) with a fundamental/push-push mode selector using a 90 nm CMOS process is presented in this letter. An innovative concept of the VCO with the mode selector is proposed to switch the fundamental or second harmonic to the RF output. The VCO demonstrates a fundamental frequency of up to 98 GHz with an output power of greater than $-8~{rm dBm}$. The phase noise of the VCO is better than $-100.8~{rm dBc}/{rm Hz}$ at 1 MHz offset frequency, and its figure-of-merit is better than $-186~{rm dBc}/{rm Hz}$. Moreover, the output frequency of the work is up to 196 GHz with a fundamental suppression of greater than $-30~{rm dBc}$ as the VCO is operated in push-push mode.