小偏压下阱中阱结构的量子隧穿特性及其实现

共振隧穿是电子的隧穿概率在某一个能量值附近以尖锐的峰值形式出现的隧穿,是目前为止最有希望应用到实际电路和系统的量子器件之一,其特点是器件的响应速度非常快。本文用传递矩阵的方法分别计算了在外加偏压下,对称双势垒、三势垒应变量子阱结构的透射系数与入射电子能量和隧穿电流与偏置电压的关系,模拟了应变多量子阱结构的隧穿系数和I-V特性曲线。计算得到隧穿电流峰值位置与实验测试值符合得很好,对于设计共振隧穿二极管并为进一步实验提供理论指导具有重要的意义。     

氮化镓基高电子迁移率晶体管栅电流输运机制研究

制备了与AlGaN/GaN高电子迁移率晶体管栅极结构与性能等效的圆形肖特基二极管结构,测量了器件的变温电流-电压特性,研究其在正向与反向偏压条件下的载流子输运过程。结果表明:(1)正向低偏压线形区的电流主要为缺陷辅助隧穿电流,而体电阻效应显著的高偏压区,经典热发射机制占主导地位;(2)AlGaN势垒层中的极化电场对器件的反向漏电流起重要作用,载流子的主要输运过程为Frenkel-Poole发射机制。     

不对称势垒对共振隧穿二极管I-V特性的影响

利用Airy函数和传输矩阵方法计算了不对称势垒厚度的InP基AlAs/InGaAs/AlAs DBS结构在偏压情况下的共振透射系数,并通过材料生长和器件工艺制作得到了共振隧穿二极管的直流I-V特性。在峰值电流密度为132kA/cm2下,获得了17.84的电流峰谷比。测试结果还表明不对称势垒厚度的RTD在偏压情况下,当电子从较薄势垒向较厚势垒穿透时,更容易获得高的电流峰谷比,反之可获得较大的负微分电阻电压区域。     

轴向应变对双势垒结构共振隧穿的影响

首先介绍了共振隧穿理论和一种新效应--介观压阻效应,对AlxGa1-xAs/GaAl/AlxGa1-xAs共振隧穿双势垒结构的轴向施加压应变作了分析,然后计算了轴向应变对垒宽和垒高的影响,对透射系数和隧穿电流用Matlab作了仿真.发现压应变可以使隧穿电流线性增加,偏压不同电流增加的速率也不同,为设计共振隧穿器件提供了理论依据.     

肖特基栅共振隧穿三极管(SGRTT)的器件模拟

使用Atlas软件模拟了肖特基栅共振隧穿三极管。通过改变发射极长度、栅极金属和上层AlAs势垒的距离以及靠近AlAs势垒的GaAs层浓度,得到器件耗尽区边界以及所对应的I-V特性,由此分析和解释了器件结构参数对器件特性的影响,最后对器件在电路中的应用予以说明。     

不对称双势垒结构中的非共振磁隧穿现象

本文系统研究了不对称GaAs/AlAs双势垒共振隧穿结构中非共振磁隧穿谱在正反偏压方向上的特征差异,并且用渡越电子沿正反方向隧穿通过双势垒结构时在势阱中停留时间的不同合理解释了实验结果。     

肖特基栅型共振隧穿晶体管的制作研究

已研制成了肖特基栅共振隧穿晶体管,在双势垒结构上蒸发铂金形成栅。通过调制准二维电子积累层的面积进而达到控制隧穿电流的目的。并对发射极正反接电压不同而出现的不同调制现象进行了分析。     

多峰I—V特性的共振隧穿量子器件

讨论了电子对双势垒共振隧穿的现象和特性,较为详细地论述了近年来发展起来的具有多峰I—V特性的共振隧穿量子器件的原理、结构和电路应用,最后展望了这类器件的发展前景。     

多峰I—V特性的共振隧穿量子器件

讨论了电子对双势垒共振隧穿的现象和特性,较为详细地论述了近年来发展起来的具有多峰I—V特性的共振隧穿量子器件的原理、结构和电路应用,最后展望了这类器件的发展前景。     

InP基RTD特性的数值模拟研究

采用基于非平衡格林函数法(Non-equilibrium Green’s function,NEGF)量子输运模拟器WinGreen对InP基共振隧穿二极管(RTD)的输运特性进行了计算模拟,分析了Ga0.47In0.53As/AlAs以及富In组份势阱双势垒结构几何参数、散射参数、发射区和集电区掺杂浓度以及隔离层厚度对InP基RTD器件I-V特性的影响。模拟结果表明,采用富In组份的势阱有利于降低峰值电压,提高发射区掺杂浓度有利于增大峰值电流密度,而散射则会导致谷值电流增大,影响其负阻特性。     

Resonant tunnelling in nc-Si/SiO2 multilayers at room temperature

Nc-Si/SiO2 multilayers were fabricated on silicon wafers in a plasma enhanced chemical vapour deposition system using in situ oxidation technology,followed by three-step thermal treatments.Carrier transportation at room temperature is characterized by current voltage measurement,and negative different conductances can be observed both under forward and negative biases,which is explained by resonant tunnelling.The resonant tunnelling peak voltage is related to the thicknesses of the nc-Si and SiO2 sublayers.And the resonant tunnelling peak voltage under negative bias is larger than that under forward bias.An energy band diagram and an equivalent circuit diagram were constructed to analyze and explain the above transportation process and properties.     

Modelling negative bias temperature instabilities in advanced p-MOSFETs

The decrease of the threshold voltage V_th of p-channel metal-oxide semiconductor field effect transistors (p-MOSFET) with ultrathin gate dielectric layers under negative bias temperature stress is studied. A degradation model is developed, that accounts for the generation of Si₃Si^√ (P_b0) centers and bulk oxide defects, induced by the tunnelling of electrons or holes through the gate dielectric layer during the electrical stress. The model predicts that V_th shifts are mainly due to the tunnelling of holes at low gate bias |V_G|, typically below 1.5 V, while electrons are mainly responsible for these shifts at higher |V_G|. Consequently, device lifetime at operating voltage, based on V_th shifts, should not be extrapolated from measurements performed at high gate bias. The impact of nitrogen incorporated at the Si/dielectric interface on V_th shifts is next investigated. The acceleration of device degradation when the amount of nitrogen increases is attributed to the increase in local interfacial strain, induced by the increase in bonding constraints, as well as to the increase in the density of Si---N---Si strained bonds, that act as trapping centers of hydrogen species released during the electrical stress. Finally, V_th shifts in p-MOSFET with Hf_ySiO_x gate layers and SiO₂/Hf_ySiO_x gate stacks are simulated, taking into account the generation of P_b0 centers induced by the injection of electrons through the structure. It is found that the transistor lifetime, based on threshold voltage shifts, is improved in SiO₂/Hf_ySiO_x gate stacks as compared to single Hf_ySiO_x layers. This finding is attributed to the beneficial presence of the SiO₂ interfacial layer, which allows the relaxation of strain at the Si/dielectric interface.     

Rediscovery of the Role of the i-Layer in n-ZnO/SiO2/p-GaN Through Observations from Both the ZnO and GaN Sides

Ultraviolet (UV)-emitting n-ZnO/SiO₂/p-GaN devices were fabricated by metalorganic chemical vapor deposition. Electroluminescence spectra of the devices were measured from both the n-ZnO and p-GaN sides. It was found that a narrow emission peak centered at ～391.3 nm was observed from the front side, while three peaks (372 nm, 380 nm, and 390 nm) emerged in the case of testing from the GaN side. To interpret this notable difference, a theoretical mechanism is proposed based on carrier accumulation and injection under forward bias voltage.     

Effects of electrical stressing in power VDMOSFETs

The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. It is shown that gate bias stressing causes significant threshold voltage shift and mobility degradation in power VDMOSFETs; the negative bias stressing causes more rapid initial changes of both threshold voltage and mobility, but the final threshold voltage shift and mobility reduction are significantly larger in devices stressed by positive gate bias. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunnelling from the charged oxide traps to interface-trap precursors Si_s–H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors Si_s–H with the charged oxide traps and H⁺ ions are proposed to be responsible for interface trap buildup.     

Electroluminescence from Au/Si/SiO2/p-Si structure

Si/SiO₂ films have been grown using the two-target alternation magnetron sputtering technique. The thickness of the SiO₂ layer in all the films was 8 nm and that of the Si layer in five types of the films ranged from 4 to 20 nm in steps of 4 nm. Visible electroluminescence (EL) has been observed from the Au/Si/SiO₂/p-Si structures at a forward bias of 5 V or larger. A broad band with one peak 650–660 nm appears in all the EL spectra of the structures. The effects of the thickness of the Si layer in the Si/SiO₂ films and of input electrical power on the EL spectra are studied systematically.     

Opto-electronic modulation spectroscopy (OEMS)

A technique is described which combines wavelength modulated monochromatic illumination with impedance measurements to discriminate the responses of bulk and surface states in the depletion regions of electronic devices. The method reveals the inherent ambiguity in conventional capacitance vs voltage and conductance vs voltage (C-V and G-V) measurements of state densities. The opto-electronic modulation spectroscopy (OEMS) spectra peak energies provide the state to band transition energies directly and these can be indexed onto an energy diagram to give the spatial positions of the responding states as well as the band with which they communicate. Measurements made on an SiO₂/n-GaAs device show an absence of surface state related peaks and suggest that surface potential pinning under positive bias may be related to bulk states emerging at the surface.     

Study of nitrogen impact on VFB-EOT roll-off by varying interfacial SiO2 thickness

Flat band voltage (V_FB) roll-off in long channel devices at thin equivalent oxide thickness (EOT) is studied on SiO₂/nitrided-HfSiO stacks. V_FB increases when SiO₂ interfacial layer thickness decreases, and charges pumping (CP) frequency sweep analysis shows higher trap density near Si/SiO₂ interface. Based on this observation, an atomic diffusion model is introduced. Higher concentration of nitrogen atom in the HfSiO(N) layer diffuses to the Si/SiO₂ interface through the SiO₂ layer in thinner SiO₂ device, and accumulates near Si/SiO₂ interface which can introduce higher density of interfacial traps. Lifetime extracted from negative bias temperature instability (NBTI), and mobility are also degraded in thinner SiO₂ devices due to the higher interfacial trap density.The V_FB roll-off can be improved by lowering nitrogen concentration in the HfSiO(N) layer from optimizing plasma nitridation pressure, decreasing post deposition anneal temperature, or using defect absorbing layer on the high-k oxide.     

The effect of small-signal AC voltages on C–V characterization and parameter extraction of SiO2 thin films

The effect of different small-signal ac voltage amplitudes on C–V curves characterized by thin SiO₂ based p-type MOS capacitor with aluminum gate is reported. When the small-signal ac voltage is comparable to the gate bias, the thickness of SiO₂ thin films extracted from the accumulation capacitance is found to be independent of small-signal ac voltage amplitudes, but the flat band voltage shift and interface state density associated with the variation of depletion layer capacitance are dependent on small-signal ac voltage amplitudes. They all increase with the small-signal ac voltage amplitudes. The experimental results reveal that the optimum small-signal ac voltage should be less than 100 mV. The mechanisms involving the depletion layer changes with small-signal ac voltages in SiO₂ thin films are also discussed in this paper.     

Investigation on bias stress effects in n-type PDI8-CN2 thin-film transistors

In this contribution, we investigate the bias stress phenomenon in n-type PDI8-CN₂ thin-film transistors fabricated by evaporation on both bare and hexamethyldisyloxane (HMDS)-treated SiO₂ gate dielectrics. Since the morphological properties of PDI8-CN₂ films are poorly influenced by the SiO₂ treatment, all the differences observed in the DC electrical response and the bias stress performances of these devices can be mainly ascribed to the interface chemistry between the dielectric and the semiconductor. In long-term bias stress experiments, performed in vacuum keeping the devices under fixed voltage polarization, the I_DS(t) decaying behavior shows to saturate when transistors on HMDS-treated substrates were considered. According to our findings, the BS physical origin is related to the occurrence of electrochemical reactions where PDI8-CN₂ molecules interact with H₂O, producing O₂ and protons (H⁺) which can initially diffuse in the SiO₂ layer barrier. Hence, the possibility that the bias stress effect in these n-type devices can be ruled by the H⁺ back-diffusion process, occurring from the SiO₂ bulk towards the dielectric-semiconductor interface during the prolonged application of positive V_GS voltages, is discussed.     

Ultra-violet photo-response characteristics of p-Si/i-SiO2/n-ZnO heterojunctions based on hydrothermal ZnO nanorods

Hydrothermal zinc oxide (ZnO) nanorod (NR)-based p-Si/n-ZnO and p-Si/i-SiO₂/n-ZnO heterojunctions were fabricated, and the effects of interfacial native SiO₂ (~4 nm) on the I-V characteristics of heterojunctions under dark and ultra-violet illumination conditions were investigated. First, the structural and optical properties of ZnO seed crystals grown by sol-gel method and hydrothermal ZnO NRs on two different substrates of p-Si and p-Si/i-SiO₂ were examined, and more improved optical and crystalline quality was obtained as revealed by photoluminescence and X-ray diffraction. The p-i-n heterojunctions showed ~3 times greater forward-bias currents and enhanced rectifying property than those of p-n junctions, which is attributed to the role of native SiO₂ in carrier confinement by promoting the electron-hole recombination current through the deep level states of ZnO crystal. The measured ratios of photocurrent to dark current of the p-i-n structure were also greater under reverse bias (92–260) and forward bias (2.3–7.1) conditions than those (28–225 for reverse bias, 1.6–6.8 for forward bias) of p-n structure, and the improved photosensitivity of the p-i-n structure under reverse bias is due to lower density of recombination centers in the ZnO NR crystals. Fabricated ZnO NR heterojunction showed repeatable and fast photo-response transients under forward bias condition of which response and recovery times were 7.2 and 3.5 s for p-i-n and 4.3 and 1.7 s for p-n structures, respectively.