板级结构参数对CSP器件焊点可靠性的影响

研究了几何因素和基板材料对无铅焊点可靠性的影响，建立了CSP封装元件的有限元模型。进行了温度循环测试，分析了焊点的应力应变情况。结果表明：基板厚度，焊点高度与焊盘直径的变化对焊点寿命有着不同的影响趋势。同时比较了FR4，Al2O3，PI材料基板与无铅焊点互连的情况，最终得出PI基板是最有利于封装器件使用的基板材料。但是由于其加工成本较高等方面的原因一般只用于高可靠性要求的军事产品领域。     

晶圆级芯片尺寸封装柔性焊点热循环可靠性

建立了晶圆级芯片尺寸封装(WLCSP)柔性无铅焊点三维有限元分析模型,基于该模型对柔性无铅焊点热循环等效应力应变进行了分析,并预测了焊点可靠性寿命。选取第一柔性层厚度、第二柔性层厚度、上焊盘直径和下焊盘直径作为关键因素,采用L16(45)正交设计了16种不同水平组合的柔性无铅焊点,获取了这些焊点的热循环等效应力数据,对等效应力数据进行了极差分析和方差分析。结果表明:在热循环加载条件下,采用柔性层结构方式能有效降低焊点内的等效应力应变;在置信度为90%的情况下,下焊盘直径和第一柔性层厚度对柔性焊点等效应力有显著影响。各因素对焊点等效应力的影响排序为下焊盘直径影响最大,其次是第一柔性层厚度,再次是第二柔性层厚度,最后是上焊盘直径。     

SMT焊点元件与基板间隙的预测及其对焊点三维形态的影响

基于能量最小原理，采用三维有限元方法，考究了片式元件与基板的间隙对ＳＭＴ焊点三维开矿的影响，利用焊点系统的能量数据，分析元件与基板的间隙。研究表明，元件与基板的间隙对焊点三维形态有重要影响，元件与基板的间隙随焊点钎料量的增加和焊盘伸出长度匠减小而增加，提出了间隙与钎料量，焊盘伸出长度关系的回归模型。     

45 nm芯片铜互连结构低k介质层热应力分析

采用铜互连工艺的先进芯片在封装过程中,铜互连结构中比较脆弱的低介电常数(k)介质层,容易因受到较高的热机械应力而发生失效破坏,出现芯片封装交互作用(CPI)影响问题.采用有限元子模型的方法,整体模型中引入等效层简化微小结构,对45 nm工艺芯片进行三维热应力分析.用该方法研究了芯片在倒装回流焊过程中,聚酰亚胺(PI)开口、铜柱直径、焊料高度和Ni层厚度对芯片Cu/低κ互连结构低κ介质层应力的影响.分析结果显示,互连结构中间层中低κ介质受到的应力较大,易出现失效,与报道的实验结果一致;上述四个因素对芯片低κ介质中应力影响程度的排序为:焊料高度＞PI开口＞铜柱直径＞Ni层厚度.     

基板焊盘的金属层结构对焊接点强度的影响

球栅阵列封装具有高密度、低成本的特点被内存领域广泛采用。在实际的使用过程中由于遭受外界各种形式的机械负载和冲击造成器件失效,典型的失效模式有5类,突出问题是焊点失效,而焊点破裂是失效的主要形式。为了改善焊点的强度,提出了焊球的快速剪切测试以及BGA器件的快速剪切测试方法来检测焊点强度,设计了4种不同金属层结构的基板焊盘,对比了不同基板焊盘的快速剪切强度和失效模式。通过数据分析和失效模式研究,证明含较厚铜层或者镍层的焊盘具有更强的焊接强度。     

基于正交试验设计的塑封球栅阵列器件焊点工艺参数与可靠性关系研究

基于正交试验设计法对塑封球栅阵列(PBGA)器件焊点工艺参数与可靠性关系进行了研究.采用混合水平正交表L₁₈(2×3⁷)设计了18种不同工艺参数组合的PBGA测试样件,进行了546小时、最大循环周数2140周的PBGA测试样件可靠性加速热循环试验.基于试验结果进行了极差分析和方差分析;研究了PBGA测试样件寿命的威布尔分布;采用有限元分析方法对热循环加载条件下PBGA焊点内应力应变分布进行了研究.试验结果表明失效焊点裂纹出现于焊点与芯片基板的交界面上.研究结果表明:样件规格对PBGA焊点可靠性有高度显著影响,芯片配重对PBGA焊点可靠性有显著的影响,焊盘直径和钢网厚度对PBGA焊点可靠性无显著影响;最优工艺参数组合为:S2D2G2M1和S2D2G2M2.有限元分析表明在热循环加载条件下PBGA器件内应力最大区域位于焊点与芯片基板的接触面上,裂纹首先在焊点与芯片基板的接触面处产生,有限元分析结果与试验结果相吻合.     

基于三维多芯片柔性封装的热应力分析

利用ANSYS软件针对一种三维多芯片柔性封装结构进行建模,通过有限元2D模型模拟该封装结构在热循环温度-40~125℃条件下产生的热应力/应变情况,讨论了芯片厚度、基板厚度、微凸点高度及模塑封材料对热应力/应变的影响。结果表明,三维多芯片柔性封装体的等效热应力发生在微凸点与芯片的连接处,其数值随着芯片厚度的减薄呈递减趋势;基板厚度也对热应变有一定的影响;增加微凸点高度有利于减小等效热应力;通过比较塑封材料得知,采用热膨胀系数较大,且杨氏模量与温度的依赖关系较强的模塑封材料进行塑封会产生较大应变。     

LGA焊点形态对焊点寿命影响的有限元分析

通过Surface Evolver软件对LGA焊点进行了三维形态预测,利用有限元数值模拟对LGA焊点在热循环条件下寿命进行了分析。研究了热循环条件下LGA焊点的应力应变分布规律,随着焊点远离元件的中心位置焊点所受到的等效应力、等效应变和塑性应变能密度逐渐增大,从而得出处于外面拐角的焊点最先发生失效的结论。基于塑性应变范围和Coffin-Manson公式计算了焊点热疲劳寿命;找出了LGA焊点形态对焊点寿命的影响规律,模板厚度一定时PCB焊盘尺寸小于上焊盘时LGA焊点的热疲劳寿命与PCB焊盘尺寸成正比,大于上焊盘时成反比,大约相等时焊点寿命最大。当PCB焊盘和模板开孔尺寸固定时,通过增大模板厚度来增加焊料体积在一定程度上可提高LGA焊点的热疲劳寿命,但是模板厚度增大到一定值时LGA焊点寿命会逐渐降低。     

倒装焊中复合SnPb焊点形态模拟

本文给出了倒装焊(flip-chip)焊点形态的能量控制方程,采用Surface Evolver软件模拟了倒装焊复合SnPb焊点(高Pb焊料凸点,共晶SnPb焊料焊点)的三维形态.利用焊点形态模拟的数据,分析了芯片和基板之间SnPb焊点的高度与焊点设计和焊接工艺参数的关系.研究表明:共晶SnPb焊料量存在临界值,当共晶SnPb焊料量小于临界值时,焊点的高度等于芯片上高Pb焊料凸点的半径值;当共晶SnPb焊料量大于临界值时,焊点的高度随共晶SnPb焊料量的增加而增加.另外,采用无量纲的形式给出了焊点高度与共晶焊料量、焊盘尺寸、芯片凸点的尺寸,芯片重量之间的关系模型,研究结果对倒装焊焊点形态的控制、工艺参数的优化和提高焊点可靠性具有指导意义.     

微尺度BGA焊点拉伸过程有限元仿真分析

建立了微尺度 BGA焊点拉伸有限元分析模型,研究了拉伸加载条件下焊点高度、直径和焊盘直径对焊点拉伸应力应变的影响。结果表明：拉伸条件下,微尺度 BGA焊点顶端和底端的应力应变要大于焊点中间部分,焊点顶部和底部位置为高应力应变区域;在只单一改变焊点高度、直径和焊盘直径其中之一的前提下,随着焊点高度、直径和焊盘直径的增加,微尺度BGA焊点内的最大应力应变均相应减小;在置信度为90%的情况下,焊点直径对拉伸应力影响最大,其次是焊盘直径,最后是焊点高度;焊点直径对焊点拉伸应力具有显著影响,焊盘直径和焊点高度对焊点拉伸应力影响不显著。     

Modeling the effect of barrier thickness and low-k dielectric on circuit reliability using 3D model

The continuous scaling down of the device size and escalating circuit speed drives the requirement for EM-resistant Cu interconnect with diffusion barrier and the low-k dielectric. The study of barrier layer thickness and low-k dielectric effect in a complete 3D circuit is necessary as the actual physical implementation of an integrated circuit in a wafer is indeed 3D in nature. This paper investigates the effect of barrier layer thickness and low-k dielectric on the circuit reliability of a complete 3D circuit model. It was found that the maximum atomic flux divergence (AFD) value increases with decreasing barrier layer thickness, which implied a shorter EM lifetime with thinner barrier. Low-k dielectric will give a higher maximum AFD due to higher stress gradient, and thus a shorter EM lifetime.     

倒装焊复合SnPb焊点应变应力分析

近年来,在微电子工业中,轻、薄、短、小是目前电子封装技术发展的趋势。因此,倒装焊技术应用越来越广,而焊点的可靠性在倒装焊技术中变得越来越重要。采用有限元软件,模拟、分析了焊点高度和下填料对焊点在热载荷作用下的应力应变值。     

Mechanical integrity evaluation of low-k device with bump shear

The mechanical integrity of low-k dielectric films has brought many process challenges in both front-end integration and back-end assembly, mostly due to possible interfacial delamination and fractures within the low-k films. From a packaging point of view, it is important to have an assessment of the integrity of the low-k stack before the device is fully assembled and the time-consuming full package evaluation is started. Some of the methods that are presently used to evaluate devices with low-k films either do not reflect the real stress situation in a package (such as 4-point bend), or introduce a mixed die-solder failure mode (such as die pull), which makes the results hard to interpret. In this paper, an evaluation method using solder bump shear is introduced. The solder joints are electroplated with a Cu stud as part of the under bump metallization. When the testing parameters are carefully optimized, bump shear can induce a failure in the low-k stack. By analyzing the maximum load of the shear test and the characteristics of the load curves, die with different interlayer dielectric materials and locations on the die with different interconnect metal densities can be effectively differentiated. A finite-element model is established and fracture mechanics methodologies are utilized to interpret the results of the bump shear.     

倒装焊器件中Cu/low-k结构热可靠性分析

利用有限元软件建立了倒装焊器件的整体模型和Cu/low-k结构的子模型,分析了在固化工艺及后续热循环条件下Cu/low-k结构的热机械可靠性。结果表明:在金属互连线与低电介质材料的交界处容易产生可靠性问题,采用low-k材料及铜互连线时均增大了两者所受最大等效应力,另外,通孔宽度对low-k及铜线的热应力影响并不明显。     

粘结层空洞对功率器件封装热阻的影响

功率器件的热阻是预测器件结温和可靠性的重要热参数,其中芯片粘接工艺过程引起的粘结层空洞对于器件热性能有很大的影响。采用有限元软件Ansys Workbench对TO3P封装形式的功率器件进行建模与热仿真,精确构建了不同类型空洞的粘结层模型,包括不同空洞率的单个大空洞和离散分布小空洞、不同深度分布的浅层空洞和沿着对角线分布的大空洞。结果表明,单个大空洞对器件结温和热阻升高的影响远大于相同空洞率的离散小空洞;贯穿粘结层的空洞和分布在芯片与粘结层之间的浅空洞会显著引起热阻上升;分布在粘结层边缘的大空洞比中心和其他位置的大空洞对热阻升高贡献更大。     

车载IGBT器件封装装片工艺中空洞的失效研究

IGBT芯片在TO-220封装装片时容易形成空洞,焊料层中空洞大小直接影响车载IGBT器件的热阻与散热性能,而这些性能的好坏将直接影响器件的可靠性。文章分析了IGBT器件在TO-220封装装片时所产生的空洞的形成机制,并就IGBT器件TO-220封装模型利用FEA方法建立其热学模型,模拟结果表明:在装片焊料层中空洞含量增加时,热阻会急剧增大而降低IGBT器件的散热性能,IGBT器件温度在单个空洞体积为10%时比没有空洞时高出28.6℃。同时借助工程样品失效分析结果,研究TO-220封装的IGBT器件在经过功率循环后空洞对于IGBT器件性能的影响,最后确立空洞体积单个小于2%,总数小于5%的装片工艺标准。     

Effect of geometry and temperature cycle on the reliability of WLCSP solder joints

The wafer level-chip-scale package (WLCSP) is designed to have external dimensions equal to that of the silicon device. This new package type is an extension of flip chip packaging technology to standard surface mount technology. The package has been targeted for low pin count (less than 30) and has high volume applications such as cellular phones, hand-held PDAs, etc. The WL-CSP is typically used without underfill and so solder joint reliability is a prime concern. Thus it is imperative to have a good understanding of the various design parameters of the package that affect the reliability of the solder joint. This paper presents the effect of geometrical parameters such as die size, die thickness, solder joint diameter and height on the reliability of solder joints. The effects of different dwell times, temperature range and ramp rates on the reliability of the solder joints is also studied by applying different temperature cycles to the package. A 16 I/O ADI WLCSP called MicroCSP is used as the primary test vehicle for the thermal cycling tests performed with different ramp/hold profiles. The energy-based model developed by Robert Darveaux is used to assess the reliability of solder joints.     

用于大功率半导体激光器的Ag-In焊料研究

大功率半导体激光器的封装对焊料选择极其重要,因为焊料导热或导电性差,激光器工作产生的大量热量使焊料焊接失效,激光器也会遭到损坏。为此,文中研究了软焊料In及其保护层Ag作为一种焊料组合,通过真空蒸发镀膜仪蒸发蒸镀Ag-In与Ag-In-Ag-In两种薄膜方式。根据微结构知识及扩散动力学与热动力学相结合讨论了Ag-In焊料产生间隙的原因,通过XRD衍射仪了解到薄膜间界面化合物AgIn2的生成可能导致表面微结构的改变,结果表明Ag层对In层易被氧化的性质起到了保护作用,多层的Ag-In焊料层可抑制大量间隙的产生,提高器件工作可靠性及稳定性。     

As-grown donor-like traps in low-k dielectrics and their impact on intrinsic TDDB reliability

Highly porous low-k dielectrics are essential for downscaling of the interconnects for 20–10 nm technologies. A planar capacitor test vehicle was used to investigate the intrinsic time dependent dielectric breakdown (TDDB) reliability of low-k dielectrics and the origin of an observed C–V hysteresis was studied. We hypothesize that the hysteresis is caused by donor-like traps present in the bulk of the low-k but not by electron/hole trapping or mobile charges. It is proposed that porogen/carbon residues are the source of these donor-like traps. Using I_leak vs. time measurements, it was found that the donor-like traps accelerate the dielectric degradation due to an enhanced E_OX, causing a localized partial breakdown. The intrinsic TDDB reliability of the low-k film was improved by adding a sealing layer as such layer blocked the donor-like traps discharging.