Charge trap generation in LPCVD oxides under high field stressing

The degradation of low pressure chemical vapor deposited (LPCVD) oxides, prepared using silane and tetra ethyl ortho silicate (TEOS) as the source, has been investigated under high field stressing. The LPCVD oxides exhibit enhanced conductivity for the Fowler-Nordheim tunneling current, which is modeled as an effective lowering of potential barrier at the injecting electrode. The charge to breakdown (Q_bd) of LPCVD oxides depends on both the deposition chemistry and post deposition annealing condition. The change in interface-state density (ΔD_it), flatband voltage (ΔV_fb), and gate voltage (Δ|V_g|) during constant current stressing are studied to identify the degradation mechanism. We see a very good correlation between Q_bd and Δ|V_g|, indicating that the degradation in LPCVD oxides is dominated by bulk trap generation and subsequent charge trapping. We present a detailed theoretical analysis to substantiate this     

Hot-carrier degradation of submicrometer p-MOSFETs withthermal/LPCVD composite oxide

It is shown that while gate oxides containing thermal/LPCVD composite oxide have lower defect densities than gates using only thermal oxides, they are more susceptible to hot-carrier degradation. The hot-carrier-induced degradation of composite oxides is worse in p-channel MOSFETs than in n-channel MOSFETs. This sensitivity of p-channel MOSFETs is caused by higher electron trapping levels in LPCVD oxides. For 150-Å gate technology, the hot-carrier-degradation resistance of thermal/LPCVD composite gate oxides with a 70-Å or thicker thermal oxide layer approaches that of high-quality pure thermal oxide     

栅氧化层TDDB可靠性评价试验及模型参数提取

采用恒定电压和恒定电流试验方法对20nm栅氧化层进行了TDDB可靠性评价试验，并完成了1／E模型参数提取，给出了恒定电流应力下描述氧化层TDDB退化的统计模型，较好地解释了试验结果。     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化. 实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流（SILC）的退化和Vth的退化均存在线性关系. 为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

A high-quality stacked thermal/LPCVD gate oxide technology for ULSI

By stacking thermal and high-quality LPCVD (low-pressure chemical vapor deposition) SiO₂ films, gate oxides with very low defect densities are demonstrated. Whereas previous reports suggested that a thick layer of LPCVD oxide can improve the stacked gate oxide defect density, it is demonstrated that even 25 Å of LPCVD oxide is sufficient to dramatically reduce the defect density compared to thermal oxide films. The projected scaling limit for this technology is estimated to be as low as 70 Å for the total stack thickness. An optimized thermal/LPCVD oxide technology is very promising as the gate dielectric for sub-half-micrometer CMOS technology     

Effects of AC hot carrier stress on n- and p-MOSFET's withoxynitride gate dielectrics

Effects of AC hot carrier stress on n- and p-MOSFET's with pure, NH₃-nitrided (RTN) and reoxidized nitrided (RTN/RTO) gate oxides are studied. Irrespective of the gate dielectric used, n-MOSFET's show enhanced degradation but p-MOSFET's show suppressed degradation under AC stress as compared to DC stress for the same duration. Dependence of degradation on frequency and duty cycle of gate pulse is studied. Results show that the degradation under AC stress in n-MOSFET's is suppressed whereas it is increased slightly in p-MOSFET's with the use of RTN/RTO gate oxides instead of conventional gate oxides     

热载流子应力下p-MOSFETs在低栅电压范围的统一退化模型

研究了低栅电压范围的热载流子统一退化模型.发现对于厚氧化层的p-MOSFETs主要退化机制随应力电压变化而变化,随着栅电压降低,退化机制由氧化层俘获向界面态产生转变,而薄氧化层没有这种情况,始终是界面态产生;此外退化因子与应力电压成线性关系.最后得出了不同厚度的p-MOSFETs的统一退化模型,对于厚氧化层,退化由电子流量和栅电流的乘积决定,对于薄氧化层,退化由电子流量决定.     

热载流子应力下p-MOSFETs在低栅电压范围的统一退化模型

研究了低栅电压范围的热载流子统一退化模型.发现对于厚氧化层的p-MOSFETs主要退化机制随应力电压变化而变化,随着栅电压降低,退化机制由氧化层俘获向界面态产生转变,而薄氧化层没有这种情况,始终是界面态产生;此外退化因子与应力电压成线性关系.最后得出了不同厚度的p-MOSFETs的统一退化模型,对于厚氧化层,退化由电子流量和栅电流的乘积决定,对于薄氧化层,退化由电子流量决定.     

不同厚度超薄栅氧化物MOSFET的应力诱导漏电流

研究了不同厚度的超薄栅1.9nm到3.0nm器件在恒压应力下的栅电流变化.实验结果显示应力诱导漏电流包括两个部分,一部分是由界面陷阱辅助隧穿引起的,另一部分是氧化物陷阱辅助隧穿引起的.     

Degradation of ultra-thin gate oxide LDD NMOSFET under GIDL stress

The degradation of device under GIDL(gate-induced drain leakage current)stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides.Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg.The characteristics of the GIDL current are used to analyze the damage generated during the stress.It is clearly found that the change of GIDL current before and after stress can be divided into two stages.The trapping of holes in the oxide is dominant in the first stage,but that of electrons in the oxide is dominant in the second stage.It is due to the common effects of edge direct tunneling and band-to-band tunneling.SILC(stress induced leakage current)in the NMOSFET decreases with increasing stress time under GIDL stress.The degradation characteristic of SILC also shows saturating time dependence.SILC is strongly dependent on the measured gate voltage.The higher the measured gate voltage,the less serious the degradation of the gate current.A likely mechanism is presented to explain the origin of SILC during GIDL stress.     

不同厚度超薄栅氧化物MOSFET的应力诱导漏电流

研究了不同厚度的超薄栅1.9nm到3.0 nm器件在恒压应力下的栅电流变化.实验结果显示应力诱导漏电流包括两个部分,一部分是由界面陷阱辅助隧穿引起的,另一部分是氧化物陷阱辅助隧穿引起的.     

The effect of hydrogen on trap generation, positive chargetrapping, and time-dependent dielectric breakdown of gate oxides

The effect of high-temperature (≈900°C) hydrogen on the gate oxides of MOS devices is studied. Hydrogen is introduced into devices by either high-temperature anneal or conventional process steps such as low-pressure chemical vapor deposition (LPCVD) of Si₃N₄. In all cases, measurements of high-field stress behavior show that high-temperature hydrogen steps reduce time to breakdown and increase bulk and interface trap generation, but do not affect the generation of positive charge. These results indicate that the wear-out mechanism of gate oxides at high fields is related to trap generation rather than to accumulation of positive charge     

Physical analysis of hard and soft breakdown failures in ultrathin gate oxides

The physical analysis of the ultrathin gate oxides (33 and 25 Å) after the electrical stressing, under constant voltage stress, reveals that the damage is not only limited to the oxide layer, but also to the entire gate structure. The hard breakdown failure makes catastrophic damage to the structure, whereas the analysis of soft breakdown failure reveals many of the hidden damages in the device structure. In Ti-silicided structures, the predominant failure mechanism is Ti migration to form a leakage path, as well as localized re-crystallisation of poly-Si or Si substrate near to the gate oxide. Co migration is so far not seen in Co-silicided devices. However, even for the very low current compliance levels and devices which do not show any electrical degradation after the SBD stress, localized epitaxy formation in the gate or Si substrate is observed, which could be a reliability concern.     

超薄栅n-MOSFETs热载流子寿命预测模型

对氧化层厚度为 4和 5 nm的 n- MOSFETs进行了沟道热载流子应力加速寿命实验 ,研究了饱和漏电流在热载流子应力下的退化 .在饱和漏电流退化特性的基础上提出了电子流量模型 ,此模型适用于氧化层厚度为 4— 5 nm或更薄的器件     

Optimization of Gate Leakage and NBTI for Plasma-Nitrided Gate Oxides by Numerical and Analytical Models

Reduction in static-power dissipation (gate leakage) by using nitrided oxides comes at the expense of enhanced negative-bias temperature instability (NBTI). Therefore, determining the nitrogen content in gate oxides that can simultaneously optimize gate-leakage and NBTI degradation is a problem of significant technological relevance. In this paper, we experimentally and theoretically analyze wide range of gate-leakage and NBTI stress data from a variety of plasma-oxynitride gate dielectric devices to establish an optimization scheme for gate-leakage and NBTI degradation. Calculating electric fields and leakage current both numerically and using simple analytical expressions, we demonstrate a design diagram for arbitrary nitrogen concentration and effective oxide thickness that may be used for process and IC design.     

Degradation of short-channel MOSFET's under constant current stress across gate and drain

We have employed a technique of constant current stress between the gate and drain of a MOS transistor to study the degradation of the threshold voltage, transconductance, and substrate current characteristics of the transistor. From the transistor characteristics, we propose that the degradation mechanism is a combined effect of trapping of holes in the gate oxide created by impact ionization due to the high electric field (> 8 MV/cm) across the oxide, and electron trapping phenomena. The degradation characteristics of the transistor under this constant current stress are quite similar to that observed normally due to the injection of hot electrons in the gate oxide when the transistor is biased in "ON" condition and the gate and drain voltages are selected to produce maximum substrate current.     

New method for lifetime evaluation of gate oxide damaged by plasmaprocessing

A quantitative model is proposed, clarifying the relationship between the charge-to-breakdown with constant current injection (Q_bd) and the time-to-breakdown with constant-voltage stress (t_bd) for gate oxides damaged by plasma processing. By including the dependence of Q_bd on the stress current density, one can predict the t_bd by means of counting the fraction of the lifetime expenditure; JΔt/Q_bd(J), where J is the current density at each period (Δt) under constant-voltage stressing, until the sum of the ratio is unity. The results show good agreement for the oxides of MOS capacitors with different gate areas. This method is useful for projection of the oxide lifetime     

Analysis of thin gate oxide degradation during fabrication ofadvanced CMOS ULSI circuits

The electrical characteristics uniquely associated with the thin gate oxide degradation of the advanced CMOS technology in manufacturing were determined for the first time. They were different from Fowler-Nordheim (F-N) stress, and therefore, cannot be simulated by the F-N stress. The p⁺ thin gate oxides were found to be inherently more susceptible to gate oxide degradation than the n⁺ gate oxides. The p⁺ oxide degradation is caused by a combination of the process-induced defect and plasma charging. The nature of the defect and its formation were identified by electrical and physical analysis. The defect formation was modeled. The p-channel gate oxide degradation will be worse with gate oxide scaling, and may limit the device scaling     

Hot-carrier-induced degradation in nitrided oxide MOSFETs

Hot-carrier-induced degradation in commercially prepared silicon-gate MOSFETs incorporating ammonia annealed, nitrided oxides as the gate dielectric is examined and compared with the degradation observed in similar devices incorporating conventional oxides. Nitridation at 1100°C for 2 h is observed to reduce the rate of transconductance degradation and threshold voltage increase by nearly half, compared to the oxide for stressing at both low and high gate bias, and to modify the effects of stressing on the substrate current characteristics. In contrast, nitridation at 1150°C produces both improvements and degradations in device stability depending on the parameter examined and the stress conditions. While ammonia annealing introduces nitrogen, it also appears to incorporate excess hydrogen in the dielectrics that alters charge trapping and interface-state generation so that the performance of the dielectric under electrical stress depends on the concentrations of both species     

GIDL应力下超薄栅氧LDD NMOS器件退化

The degradation of device under GIDL （gate-induced drain leakage current） stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides. Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg. The characteristics of the GIDL current are used to analyze the damage generated during the stress. It is clearly found that the change of GIDL current before and after stress can be divided into two stages. The trapping of holes in the oxide is dominant in the first stage, but that of electrons in the oxide is dominant in the second stage. It is due to the common effects of edge direct tunneling and band-to-band tunneling. SILC（stress induced leakage current）in the NMOSFET decreases with increasing stress time under GIDL stress. The degradation characteristic of SILC also shows saturating time dependence. SILC is strongly dependent on the measured gate voltage. The higher the measured gate voltage, the less serious the degradation of the gate current. A likely mechanism is presented to explain the origin of SILC during GIDL stress.