20V NLDMOS器件在关态雪崩击穿条件下的退化

对一种工作在关态雪崩击穿条件下的20V的NLDMOS器件的退化特性进行了研究。通过电流脉冲应力实验、TCAD软件仿真、以及电荷泵测试,提出了两种退化机制。第一种机制是N型漂移区中热空穴注入到氧化层中,在氧化层中形成固定正电荷;第二种机制是漂移区中界面态的增加引起的载流子迁移率下降。这两种机制都随着雪崩电流的增加而增强。     

N-LDMOS热载流子注入效应的分析和优化

研究了一种N-LDMOS器件的热载流子注入效应,分析了热载流子效应产生的机理、对器件性能以及可靠性的影响,提出了改进方法.为了降低此器件的热载流子注入效应,我们利用华润上华公司提供的ISE软件对N-LDMOS高压工艺进行模拟,根据模拟结果调整了器件结构,通过增大器件的场板长度、漂移区长度以及增加N阱与有源区的交叠长度等措施,使得相同偏置条件下,表征热载流子注入强度的物理量——器件衬底电流降为改进前的1/10,显著改善了该器件的热载流子注入效应.     

动态应力下MOS器件热载流子效应研究

研究了 MOS器件中的热载流子效应 ,在分析了静态应力下 MOSFET寿命模型的基础上 ,提出了动态应力条件下 MOSFET的寿命模型。此外 ,还研究了沟道热载流子的产生和注入与器件偏置条件的关系 ,讨论了热载流子效应对电路性能的影响。通过对这些失效因素的研究和通过一定的再设计手段 ,可以减少热载流子效应导致的器件退化     

脉冲应力增强的NMOSFET's热载流子效应研究

 本文研究了交流应力下的热载流子效应,主要讨论了脉冲应力条件下的热空穴热电子交替注入对NMOSFET's的退化产生的影响.在脉冲应力下,阈值电压和跨导的退化增强.NMOSFET's在热空穴注入后,热电子随后注入时,会有大的退化量,这可以用中性电子陷阱模型和脉冲应力条件下热载流子注入引起的栅氧化层退化来解释.本文还定量分析研究了NMOSFET's退化与脉冲延迟时间和脉冲频率的关系,并且给出了详细的解释.在脉冲应力条件下,器件的热载流子退化是由低栅压下注入的热空穴和高栅压下热电子共同作用的结果.     

脉冲应力增强的NMOSFET′s热载流子效应研究

本文研究了交流应力下的热载流子效应 ,主要讨论了脉冲应力条件下的热空穴热电子交替注入对NMOSFET′s的退化产生的影响 .在脉冲应力下 ,阈值电压和跨导的退化增强 .NMOSFET′s在热空穴注入后 ,热电子随后注入时 ,会有大的退化量 ,这可以用中性电子陷阱模型和脉冲应力条件下热载流子注入引起的栅氧化层退化来解释 .本文还定量分析研究了NMOSFET′s退化与脉冲延迟时间和脉冲频率的关系 ,并且给出了详细的解释 .在脉冲应力条件下 ,器件的热载流子退化是由低栅压下注入的热空穴和高栅压下热电子共同作用的结果     

深亚微米MOS器件的热载流子效应

对深亚微米器件中热载流子效应(HCE)进行了研究.还研究了沟道热载流子的产生和注入以及与器件工作在高栅压、中栅压和低栅压三种典型的偏置条件的关系.在分析热载流子失效机理的基础上,讨论了热载流子效应对电路性能的影响.提出影响晶体管热载流子效应的因素有:晶体管的几何尺寸、开关频率、负载电容、输入速率及晶体管在电路中的位置.通过对这些失效因素的研究并通过一定的再设计手段,可以减少热载流子效应导致的器件退化.     

深亚微米MOS器件的热载流子效应

对深亚微米器件中热载流子效应(HCE)进行了研究.还研究了沟道热载流子的产生和注入以及与器件工作在高栅压、中栅压和低栅压三种典型的偏置条件的关系.在分析热载流子失效机理的基础上,讨论了热载流子效应对电路性能的影响.提出影响晶体管热载流子效应的因素有:晶体管的几何尺寸、开关频率、负载电容、输入速率及晶体管在电路中的位置.通过对这些失效因素的研究并通过一定的再设计手段,可以减少热载流子效应导致的器件退化.     

深亚微米MOS器件的热载流子效应

对深亚微米器件中热载流子效应 (HCE)进行了研究 .还研究了沟道热载流子的产生和注入以及与器件工作在高栅压、中栅压和低栅压三种典型的偏置条件的关系 .在分析热载流子失效机理的基础上 ,讨论了热载流子效应对电路性能的影响 .提出影响晶体管热载流子效应的因素有 :晶体管的几何尺寸、开关频率、负载电容、输入速率及晶体管在电路中的位置 .通过对这些失效因素的研究并通过一定的再设计手段 ,可以减少热载流子效应导致的器件退化 .     

低压5V pMOS器件在不同栅偏置应力下的热载流子注入退化机理研究

研究了低压pMOS器件热载流子注入HCI（hot-carrier injection）退化机理,分析了不同的栅压应力下漏极饱和电流（Idsat）退化出现不同退化趋势的原因。结合实测数据并以实际样品为模型进行了器件仿真,研究表明,快界面态会影响pMOS器件迁移率,导致Idsat的降低;而电子注入会降低pMOS器件阈值电压（Vth）,导致Idsat的上升。当栅压为-7.5V时,界面态的产生是导致退化的主要因素,在栅压为-2.4V的应力条件下,电子注入在热载流子退化中占主导作用。     

pMOS器件的热载流子注入和负偏压温度耦合效应

研究了在热载流子注入HCI(hot-carrier injection)和负偏温NBT(negative bias temperature)两种偏置条件下pMOS器件的可靠性.测量了pMOS器件应力前后的电流电压特性和典型的器件参数漂移,并与单独HCI和NBT应力下的特性进行了对比.在这两种应力偏置条件下,pMOS器件退化特性的测量结果显示高温NBT应力使得热载流子退化效应增强.由于栅氧化层中的固定正电荷引起正反馈的热载流子退化增强了漏端电场,使得器件特性严重退化.给出了NBT效应不断增强的HCI耦合效应的详细解释.     

Hot-carrier-induced on-resistance degradation of step gate oxide NLDMOS

The hot-carrier-induced on-resistance degradations of step gate oxide NLDMOS(SG-NLDMOS) transistors are investigated in detail by a DC voltage stress experiment,a TCAD simulation and a charge pumping test.For different stress conditions,degradation behaviors of SG-NLDMOS transistors are analyzed and degradation mechanisms are presented.Then the effect of various doses of n-type drain drift(NDD) region implant on R_(on) degradation is investigated.Experimental results show that a lower NDD dosage can redu...     

HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (V_GS) and high drain voltage (V_DS), reduction of the ON-resistance (R_ON) is observed. At stress times at which R_ON almost reaches its constant level, an increase of the drain leakage in OFF state (V_DS = −60 V, V_GS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.     

SiC衬底上栅长70 nm fT / fmax >160 GHz的InAlN/GaN HEMTs器件

在SiC衬底上制备了InAlN/GaN 高电子迁移率晶体管（HEMTs）,并进行了表征。为提高器件性能,综合采用了多种技术,包括高电子浓度,70 nm T型栅,小的欧姆接触电阻和小源漏间距。制备的InAlN/GaN器件在栅偏压为1 V时得到的最大饱和漏电流密度为1.65 A/mm,最大峰值跨导为382 mS/mm。70 nm栅长器件的电流增益截止频率fT和最大振荡频率fmax分别为162 GHz和176 GHz。     

Investigation of high-K gate stacks with epitaxial Gd2O3 and FUSI NiSi metal gates down to CET=0.86 nm

Novel gate stacks with epitaxial gadolinium oxide (Gd₂O₃) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10^–7 A cm^–2 are observed at a capacitance equivalent oxide thickness of CET=1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd₂O₃ thickness of 3.1 nm yield current densities down to 0.5 A cm⁻² at V_g=+1 V. The extracted dielectric constant for these gate stacks ranges from k=13 to 14. These results emphasize the potential of NiSi/Gd₂O₃ gate stacks for future material-based scaling of CMOS technology.     

High mobility compressive strained Si0.5Ge0.5 quantum well p-MOSFETs with higher-k/metal-gate

Strained SiGe quantum well p-MOSFETs with LaLuO₃ higher-k dielectric were fabricated and characterized. The strained Si/strained Si_0.5Ge_0.5/strained SOI heterostructure transistors showed good output and transfer characteristics with an I_on/I_off ratio of 10⁵. The extracted hole mobility shows an enhancement of about 2.5 times over Si universal hole mobility and no degradation compared to HfO₂ or even SiO₂ gate dielectric devices.     

Damascene TiN-Gd2O3-gate stacks: Gentle fabrication and electrical properties

In this work, we present MOS capacitors and field effect transistors with a crystalline gadolinium oxide (Gd₂O₃) gate dielectric and metal gate electrode (titanium nitride) fabricated in a gentle damascene gate last process. Details of the gate last process and initial results on MOS devices with equivalent oxide thicknesses (EOT) of 3.0 nm and 1.5 nm, respectively, are shown.     

Leakage current variation during two different modes of electrical stressing in undoped hydrogenated n-channel polysilicon thin film transistors (TFTs)

Leakage current evolution during two different modes of electrical stressing in hydrogenated-undoped n-channel polysilicon thin film transistors (TFTs) is studied in this work. On-state bias stress (high drain bias and positive gate bias) and off-state bias stress (high drain bias and negative gate bias) were performed in order to study the degradation of the leakage current. It is found that during off-state bias stress the gate oxide is more severely damaged than the SiO₂-polySi interface. In contrast, during on-state bias stress, two different degradation mechanisms were detected which are analyzed.     

Characterization of impact of process options in Germanium-On-Insulator (GeOI) high-k & metal gate pMOSFETs by low-frequency noise

The impact of technological processes on Germanium-On-Insulator (GeOI) noise performance is studied. We present an experimental investigation of low-frequency noise (LFN) measurements carried out on (GeOI) PMOS transistors with different process splits. The front gate is composed of a SiO₂/HfO₂ stack with a TiN metal gate electrode. The result is an aggressively reduced equivalent oxide thickness (EOT) of 1.8 nm. The buried oxide is used as a back gate for experimental purposes. Front and back gate interfaces are characterized and the slow oxide trap densities are extracted. The obtained values are comprised between 5 × 10¹⁷ and 8 × 10¹⁸ cm⁻³eV⁻¹. No correlation between front interface trap density and front interface mobility is observed. We underline a strong correlation between rear interface trap density and rear interface mobility degradation. The impact of Ge film thickness is equally studied. For thin films, the measured drain-current noise spectral density shows that LFN can be described by the carrier fluctuation model from weak to strong inversion. For thicker film devices, in weak inversion the LFN can be described by the mobility fluctuation model and in strong inversion the LFN is described by the carrier fluctuation model. The α_H parameter for these devices is 1.2 × 10⁻³. These results are significant for the future development of GeOI technologies.     

半开态直流应力作用下AlGaN/GaN高电子迁移率晶体管的失效机制分析

本文研究了半开态直流应力条件下,AlGaN/GaN高电子迁移率晶体管的退化机制。应力实验后,器件的阈值电压电压正漂,栅漏串联电阻增大。利用数据拟合发现,沟道电流的退化量与阈值电压及栅漏串联电阻的变化量之间有密切的关系。分析表明,阈值电压的退化是引起饱和区沟道电流下降的主要因素,对于线性区电流,在应力开始的初始阶段,栅漏串联电阻的增大导致线性区电流的退化,随后沟道电流退化主要由阈值电压的退化引起。分析表明,在半开态应力作用下,栅泄露电流及热电子效应使得电子进入AlGaN层,被缺陷俘获,进而导致沟道电流退化。其中反向栅泄露电流中的电子被栅电极下AlGaN层内的缺陷俘获,导致阈值电压正漂;而热电子效应则使得栅漏串联区电阻增大。