基于关键路径延时检测的自适应电压缩减技术

为了减小传统的最差情况设计方法引入的电压裕量,提出了一种变化可知的自适应电压缩减(AVS)技术,通过调整电源电压来降低电路功耗.自适应电压缩减技术基于检测关键路径的延时变化,基于此设计了一款预错误原位延时检测电路,可以检测关键路径延时并输出预错误信号,进而控制单元可根据反馈回的预错误信号的个数调整系统电压.本芯片采用SMIC180 nm工艺设计验证,仿真分析表明,采用自适应电压缩减技术后,4个目标验证电路分别节省功耗12.4％,11.3％,10.4％和11.6％.     

基于自适应DVFS的SoC低功耗技术研究

对便携式系统设备而言,在采用目前90 nm和130 nm工艺进行新的系统级芯片(SoC)设计中,对整个系统功耗的优化变得与性能和面积的优化同等重要.为此,简单介绍了涵盖静态功耗和动态功耗的低功耗技术,同时提供了一种能够通过使用前向预测反馈的动态电压频率调节(DVFS)系统,并对该技术的可行性进行了建模分析,验证了自适应DVFS方式的有效性,同时也给出了评估DVFS仿真的有效途径.     

超深亚微米数字电路的低功耗设计

随着集成电路逻辑复杂度日益提高,而工艺尺寸进入了超深亚微米数量级,低功耗设计已经成为整个SOC设计中关键的问题之一.电源电压是影响功耗的最重要因素,而阈值电压、体偏压和时钟频率也对功耗有影响.目前,对于数字电路,已经研发出一些有效地进行功耗管理,降低功耗的技术,并已应用于具体项目中.本文首先综述性地介绍几种低功耗设计方法,包括:多阈值电压CMOS技术;多电源电压;门控时钟;动态电压频率调制;动态体偏压调制;加入电源门控、以及状态可保持的电源门控技术,并逐一讨论了它们对降低功耗的具体作用.最后,针对最新的基于通用功耗格式的状态保持电源门控技术,本文概述其实现步骤.     

一种基于电压窗口技术的超低功耗SAR ADC

本文提出了一种应用于生物医学的超低功耗逐次逼近型模数转换器(SAR ADC).针对SAR ADC主要模块进行超低功耗设计.数模转换(DAC)电路采用vcm-based以及分段电容阵列结构来减小其总电容,从而降低了DAC功耗.同时提出了电压窗口的方法在不降低比较器精度的情况下减小其功耗.此外,采用堆栈以及多阈值晶体管结构来减小低频下的漏电流.在55nm工艺下进行设计和仿真,在0.6V电源电压以及l0kS/s的采样频率下,ADC的信噪失真比(SNDR)为73.3dB,总功耗为432nW,品质因数(FOM)为11.4fJ/Conv.     

高电源电压抑制、低功耗片上低压差线性稳压器的研究与设计

为了能更适合于片上集成,在提供稳定电压的同时降低输入电压的噪声,设计了一种新型片上CMOS低压差线性稳压器(LDO),其显著特点是静态电流很小,在3.3V供电电压下,只有10μA的静态电流,功耗很小,适合于片上低功耗集成使用.同时,对LDO的电源电压抑制(PSR)进行了改进,提出了一种有效地使PSR提高的方法,使PSR低频下达到了大约-45dB,最差的情况也能达到-20dB左右,对输入电源的纹波噪声有比较好的抑制作用,更加适合于对噪声敏感的电路集成.     

基于嵌入式处理器的系统级低功耗管理研究

针对嵌入式系统低功耗设计问题,分析了动态功率管理DPM和动态电压/频率调节DVFS两种嵌入式功耗管理策略,并提出了系统级低功耗控制框架.讨论了基于嵌入式处理器i.MX1硬件平台实现系统级功耗控制方案,并给出了具体的设计方法.实际应用表明,该设计方案可有效降低系统能耗.     

一种低电源电压的多通道UART设计

为了满足复杂控制场合中多点通讯、低功耗、高速率以及低错误率等的要求,提出了一个低电源电压的多通道通用异步收发器(URAT,Universal Asynchronous Receiver and Transmitter)设计方案。每个通道独立控制,发送端和接收端配置的FIFO(First In First Out)在高速数据传输期间可临时存储数据以免数据丢失。采用自上而下的设计方法,使用Cadence工具进行合成与仿真。测试结果表明,该电路满足设计要求,仿真波形验证了数据收发的完整性。     

一种宽电源电压的高精度带隙基准电路的设计

设计了一种宽电源电压的高精度带隙基准电路.在综合考虑精度、电源抑制比(PSRR)、宽电源电压要求和功耗等因素的基础上,采用了一种由基准电压偏置的,增益和电源抑制比大小相近的运算放大器解决方案.设计采用CSMC 0.5μm CMOS工艺,电源为3.3V. Cadence Spectre 仿真表明,当温度在 -40 ℃～125 ℃,电源电压在2.56V～8V时,输出基准电压平均值为1.290V,变化0.793mV,有效温度系数为3.72ppm/ ℃;室温下,在低频时具有-97dB的PSRR,在100kHz时为-69dB,功耗为180μW.     

一种新颖的微处理器电源监控芯片的设计

介绍了一种多功能、低功耗微处理器电源监控芯片的设计方法.此芯片集成了带隙基准电压源、电压比较器、时基振荡、看门狗模块.文中分别对系统中各个模块做了介绍,特别是带隙基准电压源和时基振荡这两个重要模块.其中,带隙基准电压源温度系数只有12 ×10-6,芯片整体功耗电流不超过30 μA.     

一种低功耗系统芯片的实现流程

随着半导体工艺技术的进步,系统芯片的集成度越来越高,功耗成为重点考虑的因素之一,尤其用于便携式设备中。本文描述了一种多电源、多电压低功耗系统芯片的实现流程。该流程基于IEEE1801(UPF)标准,采用Synopsys和Mentor Graphics公司的EDA工具,方便地实现了RTL-GDSII的整个过程。     

电压调节技术用于SoC低功耗设计

针对便携设备在SOC系统设计中的功耗问题，通过电压调节和电压控制的方法来达到降低功耗的目的。可以用两种方法来实现，一种是开环电压调节(动态)，另一种是闭环(自适应)电压控制的方法。     

A miniature high-efficiency fully digital adaptive voltage scaling buck converter

A miniature high-efficiency fully digital adaptive voltage scaling (AVS) buck converter is proposed in this paper. The pulse skip modulation with flexible duty cycle (FD-PSM) is used in the AVS controller, which simplifies the circuit architecture (<170 gates) and greatly saves the die area and the power consumption. The converter is implemented in a 0.13-μm one-poly-eight-metal (1P8 M) complementary metal oxide semiconductor process and the active on-chip area of the controller is only 0.003 mm², which is much smaller. The measurement results show that when the operating frequency of the digital load scales dynamically from 25.6 MHz to 112.6 MHz, the supply voltage of which can be scaled adaptively from 0.84 V to 1.95 V. The controller dissipates only 17.2 μW, while the supply voltage of the load is 1 V and the operating frequency is 40 MHz.     

Fast and energy-efficient low-voltage level shifters

This paper presents two novel low-voltage level shifter designs: one based on cross-coupled PMOS transistors and the other using current mirror structure. These two level shifters are designed to address the problems of the existing state-of-the-art level shifters. Simulation at 65 nm shows that both of the proposed level shifters achieve significantly better performance (up to 12×) and energy consumption (up to 8×) than the state-of-the-art level shifters with similar or less area consumption while operating from near-threshold to super-threshold region, making them optimal for level shifting in low-power systems with multiple scalable voltage domains.     

Reward-based voltage scheduling for dynamic-priority hard real-time systems

Reward-based scheduling has been investigated for flexible applications in which an approximate but timely result is acceptable. Meanwhile, significant research efforts have been made on voltage scheduling which exploits the tradeoff between the processor speed and the energy consumption. In this paper, we address the combined scheduling problem of maximizing the total reward of hard real-time systems with a given energy budget. We present an optimal off-line algorithm and an efficient on-line algorithm for jobs with their own release-times/deadlines under Earliest-Deadline-First (EDF) scheduling. Experimental results show that the solution computed by the on-line algorithm is no more than 14% worse than the theoretical optimal solution obtained by the optimal off-line algorithm. This research was supported by the MIC (Ministry of Information and Communication), Korea, under the ITRC (Information Technology Research Center) support program supervised by the IITA (Institute of Information Technology Assessment). A preliminary version of this article was presented at Real-Time and Embedded Computing Systems and Applications (RTCSA’04).     

Sensor based adaptive voltage scaling on FPGAs: Calibration and parametrization

The impacts of aging and process variations on the performance of VLSI systems is increasing with each process generation. The conventional way to counteract them are extensive guard bands, which are calculated at system design time. Hence, they are necessarily worst case guard bands, i.e., most often too pessimistic. Current research tries to mitigate this by means of in-situ performance measurement based adaptive voltage scaling (AVS). The performance measurement is typically determined by means of dedicated sensors or canary logic. The parametrization of such AVS systems relies on assumptions regarding the relative behavior of the sensor and the application logic. Most published approaches use manually gained empirical data for this purpose. However, an automatic calibration procedure is needed for the practical application of these approaches. We propose such an automated calibration procedure and evaluate it on multiple FPGAs to consider the effects of aging and process variation. Furthermore, we use two designs to cover leakage power and dynamic power dominated scenarios. We achieve average power savings of 67% for a leakage dominated design and 48% for a test case with dominant dynamic power. Furthermore, we investigate the limitations of AVS systems regarding their capability to counteract fast disturbances, e.g., voltage drop.     

Energy minimization by exploiting data redundancy in real-time wireless sensor networks

In this paper, we devise scheduling algorithms to minimize energy consumption in Real-time Wireless Sensor Networks (WSNs) by leveraging the energy-delay tradeoff. Spatial and temporal correlation exhibited by WSNs can be exploited to reduce energy consumption. Previous research works attempt to exploit this correlation by way of aggregation or adaptive sampling. We propose determination of the data correlation at each node by way of local computation and propose avoiding transmission of significantly similar data. This can lead to unused time slots at runtime (dynamic slack) which can be traded off for energy savings. Our approach uses techniques namely Dynamic Voltage Scaling (DVS) and Dynamic Modulation Scaling (DMS), which utilize the slack generated dynamically to reduce energy consumption in a real-time environment. We propose heuristics with varying complexities for efficient slack management. We evaluate the performance of these heuristics by simulating diverse network conditions while incorporating different overheads. Our results show that the proposed heuristics can achieve energy savings up to 40% more than the baseline algorithms employing DVS and DMS, and, can achieve performance competitive with a Clairvoyant algorithm under network scenarios with high volume of redundant messages.     

Low-energy GALS NoC with FIFO—Monitoring dynamic voltage scaling

In this paper we propose two dynamic voltage scaling (DVS) policies for a GALS NoC, which is designed based on fully asynchronous switch architectures. The first one is a history-based DVS policy, which exploits the link utilization and adjusts the voltages of different parts of the router among a few voltage levels. The second one is a FIFO-adaptive DVS, which uses two FIFO threshold levels for decision making. It judiciously adjusts supply voltage of each switch among only three voltage levels. The introduced architecture is simulated in 90 nm CMOS technology with accurate Spice simulations. Experimental results show that the FIFO-adaptive DVS not only lowers the implementation cost, but also in a 86 % saturated network achieves 36 % energy-delay product (ED) saving compared to the DVS policy based on link utilization.     

A Dynamic Voltage Scaling Algorithm for Dynamic Workloads

Dynamic Voltage Scaling (DVS) is a promising method to achieve energy saving by slowing down the processor into multiple frequency levels in battery-operated embedded systems. However, the worst case execution time (WCET) of the tasks scheduled by DVS must be known ahead of time to ensure their schedulability. In reality, a system’s workloads may change significantly without satisfying any prediction. In other words, a task’s WCET may not provide useful information about its future real execution time (RET). This paper presents a novel Dynamic-Mode EDF scheduling algorithm when workloads change significantly. One of the Single-Mode, Dual-Mode, and Three-Mode frequency setting formats can be applied, based on the RET and the accumulated slack at run-time. Only one combination of the number of modes/speeds, speed-switching transition points, and the frequency scaling factor for each mode can lead to the best energy saving. Experimental results show that, given an RET pattern, our Dynamic-Mode DVS algorithm achieves an average 15% energy savings over the traditional two-mode DVS scheme on hard real-time systems. Additionally, we also consider speed-switching or energy transition overhead, and implement a preliminary test of our proposed algorithm. With a less aggressive voltage scaling strategy (fewer speed changes for each job), deadlines can still be strictly satisfied and an average of 14% energy consumption saving over a non-DVS scheme is observed.