A Comparative Study of a Dielectric‐Defined Process on AlGaAs/InGaAs/GaAs PHEMTs

We report on the fabrication of an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) using a dielectric‐defined process. This process was utilized to fabricate 0.12 μm × 100 µm T‐gate PHEMTs. A two‐step etch process was performed to define the gate footprint in the SiN_x. The SiN_x was etched either by dry etching alone or using a combination of wet and dry etching. The gate recessing was done in three steps: a wet etching for removal of the damaged surface layer, a dry etching for the narrow recess, and wet etching. A structure for the top of the T‐gate consisting of a wide head part and a narrow lower layer part has been employed, taking advantage of the large cross‐sectional area of the gate and its mechanically stable structure. From s‐parameter data of up to 50 GHz, an extrapolated cut‐off frequency of as high as 104 GHz was obtained. When comparing sample C (combination of wet and dry etching for the SiN_x) with sample A (dry etching for the SiN_x), we observed an 62.5% increase of the cut‐off frequency. This is believed to be due to considerable decreases of the gate‐source and gate‐drain capacitances. This improvement in RF performance can be understood in terms of the decrease in parasitic capacitances, which is due to the use of the dielectric and the gate recess etching method.     

Low-noise metamorphic HEMTs with reflowed 0.1-/spl mu/m T-gate

A 0.1-/spl mu/m T-gate fabricated using e-beam lithography and thermally reflow process was developed and applied to the manufacture of the low-noise metamorphic high electron-mobility transistors (MHEMTs). The T-gate developed using the thermally reflowed e-beam resist technique had a gate length of 0.1 /spl mu/m and compatible with the MHEMT fabrication process. The MHEMT manufactured demonstrates a cutoff frequency f/sub T/ of 154 GHz and a maximum frequency f/sub max/ of 300 GHz. The noise figure for the 160 /spl mu/m gate-width device is less than 1 dB and the associated gain is up to 14 dB at 18 GHz. This is the first report of a 0.1 /spl mu/m MHEMT device manufactured using the reflowed e-beam resist process for T-gate formation.     

纳米级精细线条图形的微细加工

对分辨率极高的电子束光刻技术和高选择比、高各向异性度的ICP刻蚀技术进行了研究,形成一套以负性化学放大胶SAL-601为电子抗蚀剂的电子束光刻及ICP刻蚀的优化工艺参数,并利用这些优化参数结合电子束邻近效应校正等技术制备出剖面形貌较为清晰的30nm精细线条图形.     

Four-layer resist process for asymmetric gate recess

In this paper, we present an optimized four-layer resist (PMMA and its copolymers) process for the fabrication of T-shaped gates used in compound semiconductor field effect transistors (FETs). The process is capable of producing a profile which acts as both the etch mask for the wide, asymmetric recess trench as well as the liftoff mask for a T-shaped gate metal. The resist profile is achieved in a single step using electron beam lithography, eliminating the need for two separate lithography steps and the crucial alignment between them. Gate lengths of 100 nm are achieved using this process. Recess widths on the drain side of the gate range from 50 to 300 nm, and recess widths on the source side of the gate are 50 nm.     

Recessed-gate structure approach toward normally off high-Voltage AlGaN/GaN HEMT for power electronics applications

A recessed-gate structure has been studied with a view to realizing normally off operation of high-voltage AlGaN/GaN high-electron mobility transistors (HEMTs) for power electronics applications. The recessed-gate structure is very attractive for realizing normally off high-voltage AlGaN/GaN HEMTs because the gate threshold voltage can be controlled by the etching depth of the recess without significant increase in on-resistance characteristics. With this structure the threshold voltage can be increased with the reduction of two-dimensional electron gas (2DEG) density only under the gate electrode without reduction of 2DEG density in the other channel regions such as the channel between drain and gate. The threshold-voltage increase was experimentally demonstrated. The threshold voltage of fabricated recessed-gate device increased to -0.14 V while the threshold voltage without the recessed-gate structure was about -4 V. The specific on-resistance of the device was maintained as low as 4 m/spl Omega//spl middot/cm/sup 2/ and the breakdown voltage was 435 V. The on-resistance and the breakdown voltage tradeoff characteristics were the same as those of normally on devices. From the viewpoint of device design, the on-resistance for the normally off device was modeled using the relationship between the AlGaN layer thickness under the gate electrode and the 2DEG density. It is found that the MIS gate structure and the recess etching without the offset region between recess edge and gate electrode will further improve the on-resistance. The simulation results show the possibility of the on-resistance below 1 m/spl Omega//spl middot/cm/sup 2/ for normally off AlGaN/GaN HEMTs operating at several hundred volts with threshold voltage up to +1 V.     

蓝宝石衬底上槽栅型X波段增强型AlGaN/GaN HEMT

研制了一款X波段增强型AlGaN/GaN高电子迁移率晶体管(HEMT)。在3英寸(1英寸=2.54 cm)蓝宝石衬底上采用低损伤栅凹槽刻蚀技术制备了栅长为0.3μm的增强型AlGaN/GaN HEMT。所制备的增强型器件的阈值电压为0.42 V,最大跨导为401 mS/mm,导通电阻为2.7Ω·mm。器件的电流增益截止频率和最高振荡频率分别为36.1和65.2 GHz。在10 GHz下进行微波测试,增强型AlGaN/GaN HEMT的最大输出功率密度达到5.76 W/mm,最大功率附加效率为49.1%。在同一材料上制备的耗尽型器件最大输出功率密度和最大功率附加效率分别为6.16 W/mm和50.2%。增强型器件的射频特性可与在同一晶圆上制备的耗尽型器件相比拟。     

Utilization of an electron beam resist process to examine theeffects of asymmetric gate recess on the device characteristics ofAlGaAs/InGaAs PHEMTs

The DC and microwave characteristics of two sets of AlGaAs/InGaAs PHEMTs having a gate length of 0.2 μm are compared. The first set is composed of devices fabricated using a trilayer electron beam resist process for T-gate recess and metallization. The second set is composed of devices fabricated using a new four-layer electron beam resist process which enables the asymmetric placement of a T-gate in a wide recess trench. Devices fabricated using the four-layer resist process showed improved breakdown voltage, lower gate-drain feedback capacitance, lower output conductance, and higher f_max with only slight reduction of drain current and transconductance. For example, the off-state drain-source breakdown voltage increased from 5.2 to 12.5 V, and the f_max, increased from 133 to 158 GHz as the drain side cap recess, L_ud, was increased from 0 to 0.55 μm     

0.1μm T型栅PHEMT器件

通过电子束和接触式曝光相结合的混合曝光方法,并利用复合胶结构,一次电子束曝光制作出具有T型栅的PHEMT器件,并对0.1μm栅长PHEMT器件的整套工艺及器件性能进行了研究．形成了一整套具有新特点的PHEMT器件制作工艺,获得了良好的器件性能(ft=93.97GHz;gm=690mS/mm)．     

Depletion- and enhancement-mode modulation-doped field-effecttransistors for ultrahigh-speed applications: an electrochemicalfabrication technology

This paper is devoted to an electrochemical-etching-based technology for fabricating high-performance MODFETs for high-speed applications. The electrochemical etching in the gate openings is induced by the exposure of the Ni surface metal on the ohmic electrodes; it results in very slender gate-recess grooves, which are desirable for high-speed MODFETs because of the resulting achievable small gate-to-channel separation and low parasitic resistance. The technology is easy to implement, and is effective for enhancing the aspect ratio. Good control of aspect ratio is essential for achieving excellent device performance and limiting deleterious short channel effects. Successful vertical scaling, together with minimization of gate length by well-established electron-beam lithography using fullerene-incorporated electron-beam resist, leads to the realization of both optimal D- and E-mode MODFET's with ultrahigh extrinsic transconductance values and current gain cut-off frequencies. Fully passivated 0.07-μm D-MODFET's with 2.25 S/mm extrinsic transconductance and current gain cut-off frequency exceeding 300 GHz have been successful fabricated. In addition, 0.03 μm E-MODFETs with 2 S/mm transconductance and 300 GHz current gain cut-off frequency have been demonstrated. This electrochemical-etching-based technology provides both high-performance D- and E-MODFET's and, therefore, opens up the possibility to achieve ultrahigh-speed ICs based on DCFL configurations     

A novel self-aligned gate process for half-micrometer gate GaAs ICsusing ECR-CVD

A substitutional self-aligned gate MESFET process for the half-micrometer gate GaAs IC that employs techniques of sidewall formation and precise pattern reversal using ECR (electron cyclotron resonance) CVD (chemical vapor deposition) is discussed. A FET with 0.45-μm gate length showed high performance characteristics, such as a maximum transconductance of 440 mS/mm and a cutoff frequency of 39 GHz. This process has two advantages over conventional substitutional and refractory gate processes. First, it can incorporate an LDD (lightly doped drain) structure. Second, since the photoresist dummy gates are precisely reversed without using reactive ion etching (RIE) at all, the gate length is dependent only on lithography. The process was demonstrated by the preliminary fabrication of a 16 b×16 b multiplier with 50% yield. The process, with high-performance device characteristics, should fine broad applications in both half-micrometer gate level LSIs and analog ICs     

Impact of recess-etching-assisting resist-openings on the shapes ofgate grooves for short gate length InAlAs/InGaAs heterojunction FET's

When resist openings are employed to monitor the drain current of InAlAs/InGaAs-heterojunction-based FET's during wet-chemical gate recess, etching rates for InGaAs and InAlAs can be significantly modified by the exposure of the surface metal on the nonalloyed ohmic electrodes to citric-acid-based etchants. Surface metal of Ni enhances the recess etching rate to a degree that is much higher than that in its absence. With nonselective citric acid-based etchant, the presence of Pt surface metal, however, leads to a preferential etching of InGaAs over InAlAs. This behavior of selective etching is attributed to the excess oxidation of InAlAs induced by the high electrode potential of Pt via electrochemical effects. This investigation discloses that the selection of the surface metal that lies beneath the resist openings can be very important if gate recess grooves with desired shapes are to be fabricated     

Electron-beam fabrication of submicrometer bipolar transistors for high-frequency low-current operation

A submicrometer device technology has been developed for the design and fabrication of bipolar transistors capable of high-frequency operation at low currents. Direct write electron-beam lithography is used with a single-level resist process that is compatible with high dose ion implants and dry etching, and is capable of producing feature sizes to at least the 0.5-µm level. A low temperature local oxidation process is used to minimize parasitic capacitances. Both process and device models are used in the design, which must consider the two-dimensional nature of the base-emitter region, since for these structures, the emitter junction depth is comparable in size to the emitter width. Data are presented and compared on 0.5-, 0.75-, and 1.0-µm devices.     

多能点X射线透射光栅的制作技术

针对X射线自支撑透射光栅在多能点单色成像光栅谱仪中的应用,采用电子束和光学匹配曝光、微电镀和高密度等离子体刻蚀技术,成功制备了周期为500nm、金吸收体厚度为350nm、占空比接近1∶1,满足三个能点成像需求的2000lp/mm X射线自支撑透射光栅。首先利用电子束光刻和微电镀技术制备金光栅图形,然后采用紫外光刻和微电镀技术制作自支撑结构,最后通过腐蚀体硅和感应耦合等离子体刻蚀聚酰亚胺完成X射线自支撑透射光栅的制作。在电子束光刻中,采用几何校正和高反差电子束抗蚀剂实现了对纳米尺度光栅图形的精确控制。实验结果表明,同一个器件分布的三块光栅占空比合理,栅线平滑,可以满足单能点单色成像谱仪的要求。     

Design and fabrication of a GaAs vertical MESFET

Vertically oriented GaAs MESFET's were fabricated on thick epitaxial conductive layers grown by molecular-beam epitaxy on a semi-insulating substrate. The vertical channel pattern was defined by electron-beam lithography and included structures as small as 0.3- 0.4 µm on a total period of 1.0 µm. The vertical channels were formed by reactive ion etching, and the gate contact was formed by dual-angle evaporation. The top ohmic contacts were interconnected by a metal bridge supported by a dielectric layer. The drain characteristics displayed a drain punchthrough effect, indicating that a very short gate length was achieved. Microwave measurements indicated a maximum oscillation frequency of 12 GHz.     

Investigation of the Process of Plasma Through Etching of HkMG Stack of Nanotransistor with a 32-nm Critical Dimension

The processes of plasma etching of stack layers to form a structure of a metal gate of a nanoscale transistor with a dielectric with a high level of dielectric permittivity (HkMG) are investigated. A resist mask formed by fine-resolution electron-beam lithography is used in the etching. The plasma etching of the stack’s layers is carried out in one technological etching cycle without a vacuum break. The sequential anisotropic etching process of the stack of polysilicon, tantalum nitride, and hafnium nitride, as well as the etching process of the gate insulator based on hafnium oxide with a high degree of selectivity in relation to the underlying crystalline silicon, which guarantees the complete removal of the layer of hafnium oxide and the minimal loss of the silicon layer (not more than 0.5 nm), is investigated.     

Ion-beam etched multi-level resist technique for electroplating of submicron gold absorber patterns

A structuring process is developed which enables the fabrication of gold patterns by electroplating with a minimum linewidth of ? 0.3 μm. These patterns are used as mask patterns for X-ray lithography. They can be up to 1.6 μm thick. For this purpose, a resist pattern, which is generated by an electron beam, is transmitted to a multi-layer system by reactive ion-beam etching. The multi-layer system consists of a 2 μm thick polyimide layer, a 70 nm thick aluminum intermediate layer and a 30 nm thick gold passivation layer.With this process, X-ray masks with a polyimide membrane were produced and utilized for exposure to synchrotron radiation.     

AlGaN/GaN HEMTs with 0.2μm V-gate recesses for X-band application

正AlGaN/GaN HEMTs with 0.2μm V-gate recesses were developed.The 0.2μm recess lengths were shrunk from the 0.6μm designed gate footprint length after isotropic SiN deposition and anisotropic recessed gate dry etching.The AlGaN/GaN HEMTs with 0.2μm V-gate recesses on sapphire substrates exhibited a current gain cutoff frequency f_t of 35 GHz and a maximum frequency of oscillation f_(max) of 60 GHz.At 10 GHz frequency and 20 V drain bias,the V-gate recess devices exhibited an output power density of 4.44 W/mm with the associated power added efficiency as high as 49%.     

Submicron T-shaped gate HEMT fabrication using deep-UV lithography

A new combination of low/high/low sensitivity tri-layer (PMMA/PMIPK/PMMA) resist system was used for deep UV lithography to-fabricate submicron T-shaped gate. Gate length as narrow as 0.2 μm is achieved. GaAs HEMTs with 0.3 μm T-shaped Ti/Pt/Au gate are fabricated using this technology. The HEMT demonstrated a 0.6 dB noise figure and 13 dB associated gain at 10 GHz. This deep UV lithography process provides a high throughput and low cost alternative to E-beam lithography for submicron T-gate fabrication     

Electron beam nanolithography in AZnLOF 2020

We present a lithography process using electron beam lithography with an optical resist AZnLOF 2020 for pattern transfer. High-resolution 100 keV electron beam lithography in 400 nm layers of negative resist AZnLOF 2020 diluted 10:4 with PMGEA is realized. After the electron beam lithography process, the resist is used as a mask for reactive ion etching. We performed the transfer of patterns by RIE etching of the substrate allowing a final resolution of 100 nm. We demonstrate the patterning in an insulating layer, thus simplifying the fabrication process of various multilayer devices; proximity correction has been applied to improve pattern quality and also to obtain lines width according to their spacing. This negative resist is removed by wet etching or dry etching, could allow combining pattern for smallest size down to 100 nm by EBL techniques and for larger sizes by traditional lithography using photomask.     

p-capped GaN-AlGaN-GaN high-electron mobility transistors (HEMTs)

A novel p-capped GaN-AlGaN-GaN high-electron mobility transistor has been developed to minimize radio-frequency-to-dc (RF-DC) dispersion before passivation. The novel device uses a p-GaN cap layer to screen the channel from surface potential fluctuations. A low-power reactive ion etching gate recess combined with angle evaporation of the gate metal has been used to prevent gate extension and maintain breakdown voltage. Devices with gate lengths of 0.7 /spl mu/m have been produced on sapphire. Current-gain cutoff frequencies (f/sub /spl tau//) of 20 GHz and maximum frequencies of oscillation (f/sub max/) of 38 GHz have been achieved. Unpassivated devices demonstrated a saturated output power of 3.0 W/mm and peak power-added efficiency of 40% at 4.2 GHz (V/sub DS/ = +20 V).