A complete 400-Mb/s burst-mode data OEIC receiver

A fully integrated burst-mode GaAs MESFET optoelectronic integrated circuit (OEIC) receiver, 215 mil×109 mil, that has been designed and implemented for point-to-point data links for application as a phased-array antenna controller is described. The chip provides a low-cost means for passing 400-Mb/s antenna control information using fiber optics with a very low bit-error rate (BER). Approximately 350 source-coupled FET logic gates are present on the chip. A new data coding and timing recovery scheme that is highly tolerant to jitter over a wide bandwidth has been developed. The OEIC uses an on-chip metal-semiconductor-metal (MSM) photodiode with 0.12-A/W responsivity measured at 780 nm and was fabricated in a 1.0-mm GaAs MESFET manufacturing technology. The low capacitance semi-insulating GaAs substrate minimizes the coupling between analog and digital circuitry. The circuit operates from a single 5-V supply, consumes 1 W of power, and provides an 8-b CMOS output bus together with various utility flags. Optical sensitivity is estimated at -20 dBm for 10^-14 BER     

A high-resolution CMOS time-to-digital converter utilizing aVernier delay line

This paper describes a CMOS time-to-digital converter (TDC) integrated circuit utilizing tapped delay lines. A technique that allows the achievement of high resolution with low dead-time is presented, The technique is based on a Vernier delay line (VDL) used in conjunction with an asynchronous read-out circuitry. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. A test circuit fabricated in a standard 0.7-μm digital CMOS process is presented. The TDC contains 128 delay stages and achieves 30-ps resolution, stabilized by the DLL, with the accuracy exceeding ±1 LSB. Test results show that even higher resolutions can be achieved using the VDL method, and resolutions down to 5 ps are demonstrated to be obtainable     

A vertical-cavity surface-emitting laser appliqued to a 0.8-/spl mu/m NMOS driver

An optoelectronic integrated circuit (OEIC) composed of a vertical-cavity surface-emitting laser (VCSEL) appliqued to an NMOS drive circuit was fabricated to form an optical link from the CMOS chip. A custom NMOS circuit was designed and fabricated through the MOSIS foundry service in a standard 0.8-/spl mu/m CMOS process. InGaAs quantum-well VCSELs were grown, fabricated and tested on an n-type GaAs substrate. Next, the VCSELs underwent a substrate removal technique and were appliqued to the NMOS circuitry. The OEIC was tested at the chip level and showed an electrical to optical conversion efficiency of 1.09 mW/V. Modulation results are also discussed.     

Real-time linear time-domain network analysis using picosecondphotoconductive mixer and samplers

Ion-implanted GaAs photoconductive (PC) switches have been used as an optical-microwave frequency mixer and electrical waveform samplers in a real-time sampling system. This high fidelity system has a bandwidth of 100-GHz, time resolution of 4-ps and a measurement sensitivity of 5-μV/√(Hz). Because of this high sensitivity capability, the magnitude of the testing signal can be maintained sufficiently small to allow network analysis of a device or circuit in the linear mode without signal distortion. In this paper, a linear time-domain network analysis of a broadband monolithic microwave integrated circuit (MMIC) amplifier has been demonstrated in real-time by the optoelectronic technique. A measurement time of less than 40 μs is used to acquire waveform data. The dynamic range of the system can be further improved to 40 dB by reducing the repetition rate of the step recovery diode. Since the PC switches are fabricated with processes compatible to MMIC manufacturing, this real-time system is well-suited for on-wafer MMIC characterization     

1～7GHz全单片低噪声放大器

一种性能优异的全单片宽带低噪声反馈放大器已研制成功。此两级放大器的特点是 ,性能稳定 ,频带宽 ,噪声低 ,增益高而平坦 ,可直接由 +5 V单电源供电 ,无需外加偏置电路 ,输入输出由 MIM电容隔直 ,使用方便。它由栅长为 0 .5 μm Ga As工艺制作而成 ,所有电路元器件皆集成在 3 .0 mm× 2 .0 mm的 Ga As衬底上。经测量 ,在频率 1～ 7GHz的范围内 ,放大器增益大于 2 0 d B,带内增益波动小于± 0 .75 d B,噪声系数 NF<2 .5d B,输入输出驻波 VSWR约 2 .0 ,1分贝压缩点输出功率大于 1 4d Bm。文中介绍了放大器的设计原理和工艺过程 ,并给出了测量结果。测量结果与设计符合得很好。最后值得指出的是 76mm Ga As圆片的成品率高 ,性能一致性好。     

2-4 GHz monolithic lateral p-i-n photodetector and MESFET amplifieron GaAs-on-Si

The design, fabrication, and evaluation of broadband lateral p-i-n photodetectors monolithically integrated with multistage MESFET amplifiers on GaAs-on-Si are described. Unique features of this approach are that (a) the lateral p-i-n structure is compatible with monolithic microwave integrated circuit (MMIC) technology and (b) the p-i-n detector is fabricated directly on the GaAs buffer layer without p⁺ and n⁺ implants, thus resulting in a simplified fabrication process. The operation of the circuit is compared to that of a similar circuit fabricated on a GaAs substrate. A quantum efficiency exceeding 60% has been measured for the p-i-n detectors. The 2- to 4-GHz frequency responses of one- and two-stage p-i-n/FET preamplifiers are presented. The response varies ±3 dB over the frequency band     

用于SDH STM-64光发射机的GaAs PHEMT激光驱动器

介绍了用于SDH系统STM-64速率光发射机用的激光二极管/光调制器驱动器集成电路的设计。电路采用法国OMMIC公司的0.2μm GaAs PHEMTs工艺设计并制造,可以驱动激光二极管和电吸收式调制器。电路由输入匹配电路、预放大电路、源极跟随器、主放大电路、电容耦合电流放大器和输出电路组成。电路芯片面积1.0mm×0.9mm。测试结果表明,电路采用单一正5V电源供电,直流功耗1.4W,可以在10Gb/s速率下正常工作,眼图良好。最高工作速率高于20Gb/s,输出电压幅度2.8V。     

A 6 K-gate GaAs gate array with a new large-noise-margin SLCF circuit

A 6 K-gate GaAs gate array has been successfully designed and fabricated using a novel large-noise-margin Schottky-diode level-shifter capacitor-coupled FET logic (SLCF) circuitry and a WN/SUB x/ gate selfaligned lightly doped drain (LDD) structure GaAs MESFET process. Chip size was 8.0/spl times/8.0 mm/SUP 2/. A basic cell can be programmed as an SLCF inverter, a two-input NOR, or a two-input NAND gate. The unloaded propagation delay time was 76 ps/gate a 1.2-mW/gate power dissipation. The increases in delay time due to various loading capacitances were 10 ps/fan-in, 45 ps/fan-out, and 0.64 ps/IF. A 16-b serial-to-parallel-to-serial (S/P/S) data-conversion circuit was constructed on the gate array as an application example. A maximum operation frequency of 852 MHz was achieved at a 952-mW power dissipation, including I/O buffers.     

GaAs Ultra-High-Speed Prescaler/Phase Frequency Comparator Using LSCFL (Short Paper)

A high-speed, low-power prescaler/phase frequency comparator (PFC) medium scale integration (MSI) circuit for a phase-locked stable oscillator is designed and fabricated using GaAs MESFET low-power source-coupled FET logic (LSCFL) circuitry. The construction of the 1/64 frequency divider prescaler/PFC is designed to obtain high-speed and low-power operation. The fabrication process used is buried p-layer SAINT with a 0.5-µm gate length. The fabricated prescaler/PFC MSI circuit, mounted on a newly developed high-frequency package, operates up to 7.6 GHz with a power dissipation of 730 mW.     

Single-MMIC four-channel transmitter module for multichannelRF/optical subcarrier multiplexed communications applications

Presents a compact single monolithic microwave integrated circuit (MMIC) transmitter module for four-channel RF/optical subcarrier multiplexed (OSCM) communication applications. The developed module consists of one fully monolithic four-channel OSCM transmitter integrated circuit (IC) and four coupled-line filters. The MMIC is designed and implemented in a commercial 0.6-μm GaAs MESFET process and five-stage coupled-line filters are fabricated for each of the four channels on the module board. The module design and bit-error-rate performance are considered. This is the first fully monolithic IC transmitter module for OSCM communications applications     

A 700-MHz 24-b pipelined accumulator in 1.2-μm CMOS forapplication as a numerically controlled oscillator

To accomplish timing recovery/synthesis in high-speed communication systems, a 24-b numerically controlled oscillator (NCO) IC using a circuit design technique called true single-phase clock (TSPC) pipelined CMOS has been fabricated in a standard 1.2-μm CMOS process. The device achieves a maximum tested input clock rate of 700 MHz, which results in an output frequency tuning range from DC up to 350 MHz with a 41.7-Hz tuning resolution and a peak-to-peak phase jitter of 1.4 ns. The 1.7-mm×1.7-mm IC dissipates 850 mW with a single 5-V supply, which is substantially lower than similar ECL and GaAs devices     

Dual-chip GaAs monolithic integration Ku-bandphase-locked-loop microwave synthesizer

Two novel multifunction monolithic chips, GaAs microwave monolithic integrated circuit (MMIC) and large-scale integration (LSI) chips, have been developed to realize an extremely small and lightweight microwave synthesizer. The MMIC includes a voltage-controlled oscillator, a dual-output buffer amplifier, a balun, and dynamic/static prescalers. To integrate these functions on a single chip, each circuit has been drastically reduced in size by utilizing a uniplanar MMIC configuration. The LSI includes a dual-modulus prescalar, programmable counters, and a phase/frequency comparator. By incorporating these two monolithic chips in the structure, a Ku-band microwave synthesizer has been fabricated in an 11-mm×23-mm flat package. The synthesizer to which these multifunction chips were applied had a tuning range broader than 1 GHz in the Ku-band with a flatness within 2 dB_pp. In spite of low-Q monolithic circuitry, single-sideband (SSB) phase noise was as low as -70 dBc/Hz     

四位GaAs超高速D/A转换电路的研究

本文简要介绍了目前国际上GaAs超高速D/A转换器的研制情况。在详细分析了几种常用类型D/A转换电路工作原理的基础上,结合现有GaAs VHSIC的制作工艺条件,设计并制作了一种4位单片集成GaAs MESFET D/A转换电路。测试结果表明,该电路分辨率为4位,转换速率办1Gs/s,建立时间小于1.0ns,微分线性误差小于±1/2LSB,功耗约为20mW。     

超高速单电源GaAs判决再生电路

设计并模拟分析了光纤通信用超高速单电源 Ga As判决再生电路 ,采用非掺 SI Ga As衬底直接离子注入、1μm耗尽型 Ga As MESFET、平面电路工艺研制出单片 Ga As判决再生电路。实验测试结果表明 ,该电路可对输入信号进行正确的“0”、“1”判决 ,并经时钟抽样后 ,输出正确的数字信号 ,传输速率可达 2 .8Gbit/s,可用于覆盖 2 .5Gbit/s系列光通信系统     

Demonstration of photonically controlled GaAs digital/MMIC for RFoptical links

We report design, fabrication, and test of a monolithic GaAs optoelectronic integrated circuit (OEIC) implementing a broad-band optically driven digital/analog radio frequency (RF) interface. The integrated circuit (IC) was fabricated using a foundry-compatible enhancement/depletion metal-semiconductor field-effect transistor (MESFET) process with no added lithography steps. A single optical fiber carries externally amplitude modulated 0.85-μm light to the on-chip GaAs metal-semiconductor-metal interdigitated photodetector. RF as well as simultaneous digital information encoded at up to 10 Mb/s using a novel waveform set is transmitted over the fiber. The serial digital data is self-clocked into on-chip registers to control the RF signal chain, which includes a three-bit digital attenuator. The circuit operates in an asynchronous mode to detect digital and RF on the single optical-fiber input, control RF level, and transmit the 2-8-GHz RF to the IC's electrical output. Measurements characterizing the RF and digital performance of the IC as well as a demonstration of the full optoelectronic mixed-mode functioning of the IC are presented     

Ultra-High-Speed GaAs Monolithic Prescaler and Phase Frequency Comparator IC

A high-speed, low-power prescaler and phase frequency comparator (PFC) IC for a phase-lock stable oscillator was designed and fabricated on a single chip using GaAs MESFET BFL circuitry. The gate width of the master-slave T-type flip-flops used in designing the 1/32 frequency divider prescaler was determined by circuit simulations. The fabricated 1/32 prescaler operated up to 8.0 GHz while the fabricated monolithic prescaler and PFC IC performed stable division, and phase and frequency comparison at input frequencies up to 4.8 GHz with a chip power dissipation of only 715 mW.     

A BiCMOS active substrate probe-card technology for digital testing

An active substrate silicon probe card has been implemented by forming a polyimide membrane on a silicon substrate. The probe card combines tungsten probe tips and aluminum interconnects in the polyimide membrane with active test circuitry integrated in the substrate. A monolithic prototype of the probe card designed to enhance the capabilities of conventional digital test systems has been fabricated in a 2-μm BiCMOS technology. The benefits of the proposed probe-card technology could be further exploited by integrating the timing measurement unit of a digital tester into the probe-card substrate. An integrated tester architecture based on time digitization is described. A prototype of a tester combining a time digitizer and two test channels has been integrated in a 0.6 μm BiCMOS technology. The time digitizer in the experimental circuit employs a two-stage ring oscillator that is phase-locked to an external reference and makes use of phase interpolation to achieve a timing resolution of 90 ps     

Trimming of Microstrip Circuits Utilizing Microcantilever Air Gaps (Correspondence)

A reliable method of tuning and microwave integrated circuit (MIC) line connection which has potential up to X band has been demonstrated. The method utilizes integrable fabricated microcantilever air gaps which are cold-deformed in situ to accomplish trimming. The advantages of this concept are 1) high open-circuit impedance, 2) low short-circuit insertion loss, 3) high trim resolution, 4) low line perturbation, 5) high mechanical stability, and 6) in situ fabrication with the rest of MIC circuitry.     

LSI processing technology for planar GaAs integrated circuits

A planar GaAs integrated circuit (IC) fabrication technology capable of LSI complexity has been developed. The circuit and fabrication approaches were chosen to satisfy LSI requirements for high yield, high density, and low power. This technology utilizes Schottky-diode FET logic (SDFL) incorporating both high-speed switching diodes and 1-µ m GaAs MESFET's. Circuits are fabricated directly on semi-insulating GaAs using multiple localized implantations. Rapid progress in the development of this technology has already led to the successful demonstration of high-speed (tau_{d} sim 100ps) low-power (∼500 µW/gate) GaAs MSI (∼60-100 gates) circuits. Extension of the current MSI technology to the LSI/VLSI domain will depend critically on device yield which will be dictated by the GaAs material properties and by the fabrication processes used. The purpose of this paper is to describe a GaAs IC process technology which combines advanced planar device and multilevel interconnect structures with several LSI compatible processes including multiple localized ion implantations, reduction photolithography, plasma etching, reactive ion etching, and ion milling.