可用于CMOS图像传感器片上集成的电阻网络

为模仿视网膜中水平细胞对图像信息的处理方式,提出了一种能实现空间滤波功能的CMOS电阻网络,仅由水平电阻(HRES)和偏置电路两部分组成,其偏置电路既能提供偏置电压又可作为OTA电压跟随器.该电路结构简单、电路面积小、功耗低,更利于CMOS图像传感器的片上集成.在0.6μmDPDM标准数字CMOS工艺上完成了电路设计和性能仿真.     

应用于CMOS图像传感器的带保护LDO电路的设计

随着CMOS图像传感器(CIS)的广泛应用,低功耗、高集成化、高稳定性成为其发展趋势,低压差线性稳压器(LDO)因体积小、功耗低、噪声低及电源抑制比高等优点而满足芯片供电需求.为了避免传统电源在芯片异常时仍持续工作致使功耗增加或芯片烧毁,设计了一种可应用于CMOS图像传感器的LDO电路,并加入了LDO的保护电路结构.该保护电路具有欠压保护与过流保护的功能,并能够通过数字电路对LDO进行使能控制.基于0.11 μm CMOS工艺平台对LDO及其保护电路进行仿真与分析,完成了该工艺下电路版图的绘制和验证.     

一种CMOS图像传感器片上LVDS驱动电路设计

为满足CMOS图像传感器(CIS)图像数据高速输出的需求,提出一种适用于CIS的片上高速低电压差分信号(LVDS)驱动电路结构。首先介绍了CIS高速数据传输接口的常见类型、LVDS接口技术的起源和特点;接着根据CIS的需求特点确定了LVDS驱动电路的设计思路和结构;最后给出了驱动电路设计原理图和仿真结果,以及接收端眼图仿真结果。仿真结果表明,该LVDS驱动电路,数据传输速率可以达到500Mb/s,所有参数均满足TIA/EIA-644A接口标准的需求,接收端眼高为310mV,眼宽为0.9UI。     

基于改进关联规则的图像挖掘技术研究

图像挖掘技术与关联规则的结合在网络数据索引中占据了先机,但一些功能弊端不可避免。在这样的背景下,对关联规则的编码、特征点排列和运算方法进行改进。改进关联规则将网络数据集合转化为布尔矩阵,实行列内积运算,保留矩阵内大于或等于图像特征最小支持度的逻辑,挖掘出高频特征集合。设计基于改进关联规则的图像挖掘系统,系统包含数据采集、预处理、数据库和图像挖掘四个结构层,给出具备去噪、分压和滤波功能的图像预处理电路,并介绍了图像信息数据库结构,最后通过实验证明系统可进行高效率的图像挖掘,并且图像区分度大。     

基于FPGA实时Sobel边缘检测形态学优化设计

CMOS采集到的实时图像经过中值滤波降噪处理后,采用Sobel算子进行初步的边缘检测,并对得到的边缘图像数据进一步作数学形态学开运算优化。FPGA硬件测试结果表明,该方法抗干扰及降噪能力明显优于传统的边缘检测。     

华虹NEC 0．162微米CIS工艺成功进入量产

上海华虹NEC电子有限公司日前宣布成功开发了0．162微米CMOS图像传感器（CIS162）工艺技术,已进入量产阶段。华虹NEC和关键客户合作共同开发的CIS162工艺是基于标准0．162微米纯逻辑工艺,1．8V的核心器件,3．3V的输入输出电路。经过精细调整集成了4个功能晶体管和光电二极管的像素单元可以提供超低的漏电和高清优质的图像。而特别处理的后端布线工艺保证了像素区高敏感性,     

CMOS图像传感器总剂量辐照效应及加固技术研究进展

CMOS图像传感器(CIS)在空间辐射或核辐射环境中应用时,均会受到总剂量辐照损伤的影响,严重时甚至导致器件功能失效.文章从微米、超深亚微米到纳米尺度的不同CIS生产工艺、从3T PD(Photodiode)到4T PPD(Pinned Photodiode)的不同CIS像元结构、从局部氧化物隔离技术(LOCOS)到浅槽隔离(STI)的不同CIS隔离氧化层等方面,综述了CIS总剂量辐照效应研究进展.从CIS器件工艺结构、工作模式和读出电路加固设计等方面简要介绍了CIS抗辐射加固技术研究进展.分析总结了目前CIS总剂量辐照效应及加固技术研究中亟待解决的关键技术问题,为今后深入开展相关研究提供理论指导.     

低照度CMOS图像传感器设计与实现

设计了一种基于电容反馈跨阻放大器型（Capacitive Trans-impedance Amplifier,CTIA）像元电路与双采样（Delta Double Sampling,DDS）的低照度CMOS图像传感器系统。采用CTIA像元电路提供稳定的光电二极管偏置电压以及高注入效率,完成在低照度情况下对微弱信号的读取;同时采用数字DDS结构,通过在片外实现像元积分信号与复位信号的量化结果在数字域的减法,达到抑制CMOS图像传感器中固定图案噪声的目的,进一步提高低照度CIS的成像质量。基于0.35 m标准CMOS工艺对此基于CTIA像元电路的CMOS图像传感器芯片进行流片,像元阵列为256256,像元尺寸为16 m16 m。测试结果表明该低照度CMOS图像传感器系统可探测到0.05 lx光照条件下的信号。     

基于双积分模拟重构大动态范围CIS系统研究

提出一种采用列共用模拟重构电路和双积分三采样工作时序的CMOS图像传感器(CIS)系统架构,可实现光电响应曲线压缩和像素固定模式噪声(FPN)消除,提高传感器动态范围到83 dB,使成像质量提高.该结构具有与单采样相同的像素阵列,仅增加很小的处理电路.改进的工作时序优化了长积分、短积分和信号处理的时序分配.系统控制由FPGA实现.功能和数模混合仿真验证表明,方案是可行的.     

基于忆阻器-CMOS晶体管的逻辑电路及其应用

针对传统组合逻辑电路存在的硬件资源利用率低和功耗高等问题,提出了一种基于忆阻器和CMOS晶体管的存算一体化组合逻辑电路设计方案。利用忆阻器存算一体、结构简单、与CMOS器件兼容等特性,减少了电路元器件数量。首先利用忆阻器的非易失性和阻变特性,设计忆阻与门、或门,结合CMOS晶体管实现与非门、或非门;然后,利用器件存算一体特性,提出了4R2T结构的异或门及同或门电路;最后,基于忆阻逻辑完备集设计了乘法器电路和图像加密电路,并采用LTspice验证电路功能正确性。结果表明,相比传统电路,所设计的乘法器电路元器件数量减少了50%,具有低功耗特性;所设计的图像加密电路具有良好的加密和解密效果,提升了运算效率。     

Second-order neural core for bioinspired focal-plane dynamic image processing in CMOS

Based on studies of the mammalian retina, a bioinspired model for mixed-signal array processing has been implemented on silicon. This model mimics the way in which images are processed at the front-end of natural visual pathways, by means of programmable complex spatio-temporal dynamic. When embedded into a focal-plane processing chip, such a model allows for online parallel filtering of the captured image; the outcome of such processing can be used to develop control feedback actions to adapt the response of photoreceptors to local image features. Beyond simple resistive grid filtering, it is possible to program other spatio-temporal processing operators into the model core, such as nonlinear and anisotropic diffusion, among others. This paper presents analog and mixed-signal very large-scale integration building blocks to implement this model, and illustrates their operation through experimental results taken from a prototype chip fabricated in a 0.5-/spl mu/m CMOS technology.     

A Computational Digital Pixel Sensor Featuring Block-Readout Architecture for On-Chip Image Processing

In this paper, a computational digital pixel sensor (DPS) equipped with an on-chip image-processing capability has been developed. In order to resolve the interconnection bottleneck between the sensor array and on-chip processing units, a new block-readout architecture has been proposed and implemented on the chip. The data from the sensor array are read out in a form of a pixel block compatible to kernel image processing, and they are processed in parallel by on-chip processing units. Such an architecture has enabled us to carry out an efficient kernel processing using a linear array of single-instruction–multiple-data processing units. In order to demonstrate the advantage of such an architecture, a rank-order filtering circuit has been implemented on the chip as a case study of the on-chip image processing. In this paper, a binary-search rank-order filtering algorithm has been implemented in a simple circuitry. A proof-of-concept chip having an array of 64$times$48 pixels was designed and fabricated using a 0.35-${rm mu}hbox{m}$ CMOS technology, and the concept has been verified by the measurement of fabricated chips.      

Optic nerve signals in a neuromorphic chip I: Outer and inner retina models

We present a novel model for the mammalian retina and analyze its behavior. Our outer retina model performs bandpass spatiotemporal filtering. It is comprised of two reciprocally connected resistive grids that model the cone and horizontal cell syncytia. We show analytically that its sensitivity is proportional to the space-constant-ratio of the two grids while its half-max response is set by the local average intensity. Thus, this outer retina model realizes luminance adaptation. Our inner retina model performs high-pass temporal filtering. It features slow negative feedback whose strength is modulated by a locally computed measure of temporal contrast, modeling two kinds of amacrine cells, one narrow-field, the other wide-field. We show analytically that, when the input is spectrally pure, the corner-frequency tracks the input frequency. But when the input is broadband, the corner frequency is proportional to contrast. Thus, this inner retina model realizes temporal frequency adaptation as well as contrast gain control. We present CMOS circuit designs for our retina model in this paper as well. Experimental measurements from the fabricated chip, and validation of our analytical results, are presented in the companion paper [Zaghloul and Boahen (2004)].     

低噪声CMOS图像传感器的研究

近年来CMOS图像传感器在医疗和工业CT等领域中得到了越来越广泛的应用。作为CMOS图像传感器的前端处理电路,多通道积分器阵列的性能参数直接决定了传感器的成像质量并成为该领域的研究热点。本文的主要研究内容是低噪声探测器的研究。对芯片的测试结果表明,低噪声探测器的电路设计和版图设计均取得初步成功,基本达到预期的设计目标。     

包含交流耦合CTIA与数字CDS的CMOS图像传感器设计

设计了一种带隔直电容的交流耦合CTIA像元电路与数字相关双采样（DCDS）结构的CMOS图像传感器系统。在传统的CTIA像元电路中增加隔直电容,通过控制光电二极管的偏压,达到减小光电二极管暗电流的目的;同时采用片外数字CDS结构,通过在片外实现复位信号与像元积分信号的量化结果在数字域的减法,可以减小图像传感器像元的复位噪声和固定图案噪声（FPN）。基于0.35 m标准CMOS工艺对此CMOS图像传感器进行流片,像元阵列为256256,像元尺寸为16 m16 m。测试结果表明交流耦合CTIA像元电路可以将光电二极管的偏压控制在零偏点附近,此时其暗电流最小;采用了数字CDS结构后,图像传感器像元的时域噪声及固定图案噪声均有不同程度降低。     

A ranked order filter implementation for parallel analog processing

Order statistic filtering, the generalization of which is ranked order filtering, is needed for many image-processing functions including median filtering and mathematical morphology. Combining order statistic functionality with the parallel operation and local connectivity of array processing approaches such as the cellular nonlinear network model, has the potential for very high performance in image processing. This paper examines the implementation of programmable ranked order extraction with a very compact hardware realization of an analog current-mode ranked order filter. The considerable savings in the required circuit area, compared to other circuits, make it possible to use the structure as a building block in a massively parallel signal processing array. The operation of the circuit is analyzed in detail with the help of simulations and measurement results obtained from a test chip manufactured in a 0.18-/spl mu/m standard digital CMOS technology are also presented. The simulations and measurement results verify the correct operation of the circuit and show that it is very suitable for inclusion in every cell of a large parallel processor array. This makes many grayscale processing functions available with truly parallel operation and therefore very high performance.     

A novel monolithic ultraviolet image sensor based on a standard CMOS process

We present a monolithic ultraviolet(UV) image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists of a CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16×16 image sensor prototype chip is implemented in a 0.18μm standard CMOS logic process.The pixel and image sensor were measured. Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/(mJ/cm~2) and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications.     

3D传感器的设计与研究

3D传感器是获取双视图画面的重要手段,在3D图像交互及机器人技术中有着重要的应用前景.根据人眼仿生学原理设计3D传感器结构,并研究现场可编程门阵列FPGA对双CMOS高分辨率图像的采集与处理方法,通过同步数据采集和轮序存储法完成3D图像的获取并实时显示.     

A 100 dB Dynamic-Range CMOS Vision Sensor With Programmable Image Processing and Global Feature Extraction

A 128 times 64 pixel programmable vision sensor performs real-time analog image processing over high dynamic range images is reported. The pixel-parallel single instruction multiple data (SIMD) architecture executes real-time spatio-temporal filtering with 2.8 GOPS/mm² and large flexibility in coefficient assignment. The sensor uses time-based and pulse-based operating modalities to execute spatio-temporal filtering on images with dynamic range up to about 100 dB. The in-pixel processing is based on two operations: the absolute value of voltage difference and accumulation of partial results. Feature extraction from the entire image is also possible without the need for image dispatching, thus optimizing both processing speed and video bandwidth. The 32.6 mum square pixel, with a fill-factor of 24%, consists of two analog memories and 28 transistors. The sensor, fabricated in 0.35 mum CMOS technology, gives a fixed pattern noise (FPN) of 0.8% and power consumption of 14 mW at 3.3 V