基于TTA技术的专用处理器设计

描述了一种基于传输触发体系架构(TTA)的处理器.对其指令集的设计和体系结构的优化进行了讨论,并给出了H.264帧内预测算法的ASIP处理器设计实例,有效的克服了当前专用处理器和微处理器的局限性.实验表明:基于TTA体系结构的H.264帧内预测ASIP处理器较之通用处理器运行周期快4倍以上.     

基于字典压缩的TTA架构处理器代码压缩研究

为了有效减小程序代码尺寸、节省芯片设计面积,以一种采用Verilog HDL硬件描述语言的自主设计传输触发架构(TTA)微处理器为目标内核,研究并实现了用字典压缩算法对程序代码进行压缩和解压缩.根据TTA架构微处理器内核的特点,在不同压缩粒度上对代码压缩进行优化,并对经典的LZ78字典压缩算法进行代码压缩应用方面的改进.测试结果表明,优化的字典压缩算法改善了代码压缩效果.采用考虑字典大小的代码压缩率评估方法,实现了代码压缩率的有效评估.     

基于单一产品数据源的复杂产品设计制造协同技术研究

针对复杂产品设计制造协同过程中存在数据源不唯一的问题,提出了基于单一产品数据源的复杂产品设计制造协同技术及其层次体系结构,通过构建逻辑上统一的单一产品数据源,保证了设计制造协同数据的唯一性,并给出了分布式单一产品数据源的建立方法、单一产品数据源信息模型的构建原理及其技术实现方法,以航空发动机为验证对象,实现了基于单一产品数据源的设计制造异地协同,证明了此方法是正确和有效的.     

"龙腾(R)R2"微处理器流水线的设计及优化

32位RISC微处理器"龙腾(R)R2"是西北工业大学航空微电子中心2005年设计的一敖自主知识产权的嵌入式微处理器,采用PowerPC体系结构,六级流水线,具有独立的数据Cache和指令Cache.文章介绍"龙腾(R)R2"处理器流水线的设计思想以及优化方案,重点介绍流水线中相关的解决方案、精确异常的实现以及流水线中指令预取级的设计与实现等.     

一种基于流水线的指令Cache优化设计

在现代微处理器的设计中．Cache是整个微处理器性能的决定性因素。本文详细介绍了32位RISC微处理器“龙腾”R2中指令Cache的体系结构．着重研究了其设计和实现问题。为了提高性能,采用了预取技术和流水线技术来优化设计．仿真结果表明得到了预期的效果。     

一种嵌入式微处理器中的在线调试模块设计

文章提出了一种嵌入式微处理器的在线调试模块。这个模块可以用较少的硬件开支实现一些强大的调试功能：响应硬件和软件触发、提供开始／停止调试模式、单步调试操作、程序执行的跟踪、代码内存、外部数据存储器、SFR、内部数据存储器的读和写。文章首先介绍了嵌入式微处理器可调试模块设计的原理，其次介绍了在线调试的结构设计，最后给出结论和分析。     

基于固定指令多数据流模型的Cache设计与实现

为加速循环程序执行,提出了固定指令多数据流计算模型,并设计了一个单芯片阵列处理器体系结构.如果采用传统的数据取,将带来存储网络中大量的数据流动,随之而来的是冲突的频繁出现和不断增长的存储带宽需求.为此采用了数据打包传递技术.实践证明,这种技术可以显著减少网络冲突,降低存储带宽需求.     

高性能16位徽处理器IP软核设计

在对标准Intel 8086微处理器进行分析的基础上,本文介绍了一种与其指令集兼容、性能大幅提高的可重用16位微处理器IP软核的设计.从处理器体系结构的划分,到指令集的设计以及处理器内部各单元的设计,进行了比较详尽的阐述,并对该设计进行了软件仿真和硬件验证.该处理器采用缩短指令执行时钟周期、增加指令预取队列、改进总线接口时序和减少有效地址计算时间等系统架构的优化,使性能得到大幅度的提高;通过扩展指令集实现与标准8086、8088、80186和80188系列微处理器完全软件兼容.     

基于Balsa-Xilinx FPGA的异步设计流程

针对异步电路设计工具问题,提出了一种基于Balsa和Xilinx FP(iA的全异步设计流程.采用Balsa语言描述异步设计产生网表,导入网表在Xilinx下生成可配置文件,达到板级验证并进行布局布线后仿真分析,在完成异步电路设计的同时采用同步EDA工具验证,以实现异步设计与同步软件的结合,最后通过八位异步全加器设计实例验证该异步设计流程的可行性.     

基于嵌入式微处理器的无功调节控制器的研究

介绍一种新型的基于软开关投切技术的连续无功补偿装置,并设计出适用于该方案的基于ARM嵌入式微处理器的无功补偿控制器。采用了一种基于32位ARM7TDMI嵌入式微处理器S3C44B0X和μC/OS-Ⅱ实时操作系统内核的交流同步采样方法,设计出无功补偿控制系统,阐述了智能控制器的设计思路及实现的体系结构,从硬件和软件两方面论述了具体设计和实现过程。     

一种基于低温多晶硅TFT技术的柔性8位异步微处理器

介绍基于低温多晶硅TFT技术和采用激光退火表面刻蚀技术的柔性8位异步微处理器,并且给出了异步电路描述语言Verilog 。32,000个晶体管的微处理器在500kHz,5V的条件下消耗电流180mA,功耗是同步微处理器的30%。     

基于并行完备检测的高速异步流水线设计

为了有效地提升异步零协议逻辑(NCL)流水线的吞吐量,该文提出一种多阈值并行完备流水线。采用独特的半静态零协议阈值门建立异步组合逻辑,使数据串行传输的同时每级流水线数据处理和完备检测并行进行,以串并结合的工作方式提升吞吐量。同时新阈值门的使用降低了流水线空周期时的静态功耗。基于SMIC 0.18μm标准CMOS工艺对所提出的流水线进行了分析测试。与现有流水线比较显示,当组合逻辑为四位串行进位全加器时,新的流水线吞吐量提升62.8%,静态功耗减少40.5%,可用于高速低功耗的异步电路设计。     

一种新型低功耗异步比较器的设计方法

本文利用输入数据的统计特性,设计了两种低功耗异步比较器——异步行波比较器和提前终止异步比较器.异步行波比较器从第一个不相等的数位开始停止运算,但要把结果传到最低位,消耗部分功耗.提前终止异步比较器通过修改真值表,基于新的比较单元电路和终止判断电路,在第一个不相等的数位停止运算并立即输出比较结果,节省不必要的功耗.新设计的异步比较器和用于对比的同步比较器(BCL比较器和门控时钟比较器)均用SMIC0.18μm工艺实现.仿真结果表明,提前终止异步比较器功耗最低,与同步BCL比较器和门控时钟比较器相比,在随机数据和来自LDPC解码器的数据下,分别节省了87.1%、84.5%和37.5%、28.6%的功耗.     

Application-specific programmable control for high-performanceasynchronous circuits

The advantages of the programmable control paradigm are widely known in the design of synchronous sequential circuits: easy correction of late design errors, easy upgrade of product families to meet time-to-market constraints, and modifications of the control algorithm, even at run time. However, despite the growing interest in asynchronous (self-timed) circuits, programmable asynchronous controllers based on the idea of microprogramming have not been actively pursued. In this paper, we propose an asynchronous microprogrammed control organization (called a microengine) that targets application-specific implementations and emphasizes simplicity, modularity, and high performance. The architecture takes advantage of the natural ability of self-timed circuits to chain actions efficiently without the clock-based scheduling constraints that would be involved in comparable synchronous designs. The result is a general approach to the design of application-specific microengines featuring a programmable data-path topology that offers very compact microcode and high performance-in fact, performance close to that offered by automated hardwired controllers. In performance comparisons of a CD-player error decoder design, the proposed microengine architecture was 26 times faster than the general purpose hardware of a 280 MIPS microprocessor, over three times as fast as the special purpose hardware of a low-power macromodule based implementation, and even slightly faster than a finite state machine-based implementation     

自适应异步采样运动数据压缩算法

 针对三维运动捕获系统的广泛应用,采样频率越来越高,运动数据库日益增大带来的问题,本文提出多路信号异步采样思想对运动数据进行压缩.理论上论证了在人体运动所固有的客观及主观约束条件下采用本文提出异步采样思想比同步采样能够获取更高压缩比,并针对每一路信号提出了基于三次样条的自适应重采样算法.通过大量运动实验分析了不同运动阶段的数据可压缩性,最高压缩比达到13.24,在单个标记点误差为0.5cm时,数据解压重构毫不影响视觉效果.     

应用于智能卡的Java嵌入式微处理器核的设计

介绍了一种可直接执行Ｊａｖａ字节码的嵌入式微处理器体系结构。该处理器核实现了Ｊａｖａ卡虚拟机（ＪＣＶＭ）指令集。类ＲＩＳＣ的流水线显著加快了指令的执行速度。文中对堆栈类型指令间的数据相关问题提出了一种新的解决办法。     

Effective Timing Error Tolerance in Flip-Flop Based Core Designs

Timing errors turn to be a great concern in nanometer technology integrated circuits. This work presents a low-cost and power efficient, multiple timing error detection and correction technique for flip-flop based core designs. Two new flip-flop designs are introduced, which exploit a transition detector for timing error detection along with asynchronous local error correction schemes to provide timing error tolerance. The proposed, the Razor and the Time Dilation techniques were applied separately in the design of three versions of a 32-bit MIPS microprocessor core and the pci_bridge32 IWLS05 core, using a 90 nm CMOS technology. Comparisons based on simulation results validate the efficiency of the new design approach.     

A novel comparator featured with input data characteristic

Two types of low-power asynchronous comparators featured with input data statistical characteristic are proposed in this article. The asynchronous ripple comparator stops comparing at the first unequal bit but delivers the result to the least significant bit. The pre-stop asynchronous comparator can completely stop comparing and obtain results immediately. The proposed and contrastive comparators were implemented in SMIC 0.18 μm process with different bit widths. Simulation shows that the proposed pre-stop asynchronous comparator features the lowest power consumption, shortest average propagation delay and highest area efficiency among the comparators. Data path of low-density parity check decoder using the proposed pre-stop asynchronous comparators are most power efficient compared with other data paths with synthesised, clock gating and bitwise competition logic comparators.     

一种基于微处理器的SOC自测试方案

提出了一种基于片上微处理器和透明路径测试访问的SOC自测试方案。以片上微处理器为测试加载和响应收集比较的主体,构造透明路径并行传输测试数据,以嵌入程序控制测试过程。可以在提高测试速度的同时,降低对测试设备性能的依赖,并可以进行全速测试,所需额外面积开销较小。实验表明,该测试方案是有效的。     

A full asynchronous serial transmission converter for network-on-chips

Large transmission power consumptions and excessive interconnection lines are two shortcomings which exist in conventional network-on-chips. To improve performance in these areas, this paper proposes a full asynchronous serial transmission converter for network-on-chips. By grouping the parallel data between routers into smaller data blocks, interconnection lines between routers can be greatly reduced, which finally brings about saving of power overheads in the transmission process. Null convention logic units are used to make the circuit quasi-delay insensitive and highly robust. The proposed serial transmission converter and serial channel are implemented based on SMIC 0.18 μm standard CMOS technology. Results demonstrate that this full asynchronous serial transmission converter can save up to three quarters of the interconnection line resources and also reduce up to two-thirds of the power consumption under 32 bit data widths. The proposed full asynchronous serial transmission converter can apply to the on chip network which is sensitive to area and power.