新型4H-SiC 射频功率MESFET 大信号经验电容模型

基于4H-SiC 射频功率MESFET 器件的工作机理,提出了一种新型的大信号经验电容模型。针对此模型参数的提取采用最小二乘法和遗传算法,算法用MATLAB 语言实现,与传统算法相比,经验电容模型参数的初值估计和优化更为简单准确。提取的模型重要参数具有一定的物理意义,其他拟合参数值也具有物理量级。模型仿真结果和实测数据拟合度较好,从而验证了所提出的大信号经验电容模型的准确性。     

双极型晶体管交流模型参数的优化提取

双极型晶体管交流模型参数的优化提取包括势垒电容模型参数和正向渡越时间模型参数的优化提取.采用非线性函数最小二乘法拟合实验曲线对上述参数的提取是非常有效的.电容模型公式是由耗尽层近似理论推得的.用该电容模型公式拟合实验曲线,得到了最优的电容模型参数,计算曲线与实验曲线的误差约为1％.为了精确模拟正向渡越时间,根据实验结果对 SPICE 2G程序中的模型公式进行了修正,用修正后的模型公式拟合实验曲线,得到了最优的描述正向渡越时间的模型参数,计算曲线与实验曲线的误差为1.02％.     

GaAs MIM电容模型

阐述了无源元件在MMIC设计中的重要性及MIM电容模型参数提取的几种方法.以简化的MIM电容等效电路为基础,通过IC-CAP建模软件,建立平板电容的等效模型模拟其电学特性.根据实测数据提取相关模型参数,同时与实际测试的MIM电容值进行对比,对ADS元件库中电容模型的关键参数做了修改和验证.经过在GaAs工艺线实际流片统计、验证,该模型在40 GHz以下实测的S参数与电磁仿真结果基本吻合,平板电容的误差控制在3%以内,可用于40 GHz以下CaAs MMIC的电路设计和仿真.     

一种提取 Statz MESFET 非线性电容模型参数的方法

文章提出一种Ｓｔａｔｚ ＧａＡｓ ＭＥＳＦＥＴ非线性电容模型参数的简单方法。它基于逐点拟合和综合拟合法,并以小信号模型数据分布在电容电压特性曲线的三个区为判据,判定提取的电容模型参数的正确性。计算表明,对偏置的电容Ｃｇｘ和Ｃｇｄ数据情况,提取Ｓｔａｔｚ非线性电容模型参数较适用。     

3 nm环栅场效应管射频小信号等效电路模型

针对3 nm环栅场效应晶体管,提出了一种射频小信号等效电路模型及基于有理函数拟合的解析模型参数提取方法。首先,在关态条件下提取不受偏置影响的非本征栅/源/漏极电阻、栅到源/漏电容、衬底电容和电阻。然后,在不同偏置条件下提取受偏置影响的本征模型参数。使用Sentaurus TCAD和Matlab对器件进行仿真并拟合得到相关参数,在ADS中验证等效电路模型。结果表明,在10 MHz~300 GHz频率范围内,TCAD仿真与等效电路仿真S参数的最大误差低于2.69%,证实了所建立模型及建模方法的准确性。该项研究成果对射频集成电路设计具有参考价值。     

太赫兹平面肖特基二极管参数模型

根据太赫兹平面肖特基二极管物理结构,在理想二极管SPICE参数模型的基础上建立了二极管小信号等效电路模型。依据该二极管等效电路模型设计了基于共面波导（CPW）去嵌方法的二极管S参数在片测试结构,并对其在0.1~50 GHz、75~110 GHz频率范围内进行了高频小信号测试,利用测试结果提取了高频下二极管电路模型中各部分电容、电阻以及电感参数。将相应的高频下电容与电阻参数分别与低频经验公式电容值和直流I-V测试提取的电阻值进行了对比,并利用仿真手段对高频参数模型进行了验证。完整的参数模型以及测试手段相较于理想二极管SPICE模型和传统的参数提取方法可以更为准确地表征器件在高频下的工作状态。该建模思路可用于太赫兹频段非线性电路的优化设计。     

一种微波功率LDMOS器件非线性模型

对微波功率LDMOS器件进行测试,提出一种新的非线性模型,通过小信号参数提取,建立LDMOS的小信号模型,对多偏置下本征电容的提取,建立LDMOS本征电容的非线性模型,加入LDMOS的直流IV模型并以此为基础确立了微波功率LDMOS的大信号模型,经过此模型的LoadPull仿真及芯片测试对比,表明了该模型可以较准确地模拟LDMOS的微波特性。采用该模型设计了一种功率管放大器,通过最终测试与仿真结果对比,证明了该模型的实用性。     

短沟道薄膜全耗尽SOI/MOSFET''''s大信号电容模型

本文提出适用于短沟道薄膜全耗尽SOI器件的大信号电容模型。该模型除考虑了SOI短沟道器件中出现的速度饱和效应、DIBL效应及源漏耗尽层电荷分享效应外,还包括了SOI器件中特有的膜厚效应、正背栅耦合效应等对电容特性的影响。通过与体硅器件的二维模拟和实测电容特性以及已报道的薄膜SOI器件电容模型相比较可知,本文模型可较好地描述短沟道SOI器件的电容特性。另外,所建电容模型形式简洁,参数提取方便,因而可做为薄膜全耗尽SOI器件大信号电容模型移植到电路模拟程序(如SPICE)之中。     

短沟道薄膜全耗尽SOI/MOSFET''s大信号电容模型

本文提出适用于短沟道薄膜全耗尽SOI器件的大信号电容模型。该模型除考虑了SOI短沟道器件中出现的速度饱和效应、DIBL效应及源漏耗尽层电荷分享效应外,还包括了SOI器件中特有的膜厚效应、正背栅耦合效应等对电容特性的影响。通过与体硅器件的二维模拟和实测电容特性以及已报道的薄膜SOI器件电容模型相比较可知,本文模型可较好地描述短沟道SOI器件的电容特性。另外,所建电容模型形式简洁,参数提取方便,因而可做为薄膜全耗尽SOI器件大信号电容模型移植到电路模拟程序(如SPICE)之中。     

VDMOS等效电路的SPICE模型

分析了VDMOS器件中存在的各种寄生效应以及这些寄生效应对器件性能的影响,在此基础上建立了VDMOS等效电路的SPICE模型.通过MEDICI数值分析软件,模拟VDMOS在不同偏置条件下的电压、电流、电容特性,从而提取出VDMOS等效电路模型参数.并用SPICE软件对等效电路仿真,进行了直流分析和瞬态分析,得到等效电路的电学特性曲线图.仿真的结果与MEDICI器件模拟工具模拟结果相互比较,具有较好的一致性.     

一种基于数值模型的4H-SiC MESFET大信号建模方法

提出了一种基于数值模型的4H-SiC MESFET大信号建模方法.该方法基于4H-SiC MESFET的物理参数和结构参数,采用MEDICI的小信号正弦稳态分析法和高频小信号等效电路,模拟得到电流和电容的非线性特性,通过大信号等效电路,分析了建立4H-SiC MESFET大信号模型的途径.模拟与实验测试值的比较表明这种方法是可行的,可用于预先评估器件大信号工作时的非线性特性,指导4H-SiC MESFET的器件设计.     

AlGaN/GaN HEMT多偏置下CV特性的研究

电容电压特性是分析半导体器件性能的一个有效手段,而且是GaN HEMT器件大信号模型建模的重要步骤之一。本文提出一种多偏置电容电压的测试方法,并讨论了Cgs和Cgd的物理意义及其随偏置电压Vgs和Vds的变化规律。提出一种能够反映Cgs和Cgd特性的电容模型,与测试电容数据有很好的拟合效果,并且用器件的功率特性验证了该电容模型在非线性仿真的准确性。     

Multi-bias capacitance voltage characteristic of AlGaN/GaN HEMT

The method of multi-bias capacitance voltage measurement is presented. The physical meaning of gate-source and gate-drain capacitances in AlGaN/GaN HEMT and the variations in them with different bias con-ditions are discussed. A capacitance model is proposed to reflect the behaviors of the gate-source and gate-drain ca-pacitances, which shows a good agreement with the measured capacitances, and the power performance obtains good results compared with the measured data from the capacitance model.     

A new charge conserving capacitance model for GaAs MESFET's

We present a new charge conserving capacitance model for Gallium-Arsenide (GaAs) metal semiconductor field effect transistors (MESFET's) based on the quasi-static approximation and a proper partitioning of the channel charge between the source and the drain terminals. A total of nine so-called transcapacitances were determined by taking derivatives of the various terminal charges with respect to the voltages at source, drain, and gate. The transcapacitances are nonreciprocal, i.e., C_ij≠C_ji when i≠j, and can be organized in a 3×3 matrix incorporating Kirchhoff's current law (charge conservation) and independence of reference. The present capacitance model is valid both above and below threshold, and shows good agreement with experimental data over a wide range of gate and drain biases. The model is analytical and suitable for implementation in circuit simulators     

Base-collector junction capacitance of bipolar transistors operating at high current densities

An analytical physics-based comprehensive base-collector junction capacitance model is presented. The model, which includes high-current effects, describes the base-collector space-charge-region capacitance for all operating regions, including the saturation region in which the space-charge region becomes forward biased. The present model is compared with the depletion capacitance model and significant discrepancies are predicted. An emitter-coupled logic gate circuit is used to demonstrate the practical usefulness of the model.     

A simple model for the overlap capacitance of a VLSI MOS device

A simple approximate analytical expression for the overlap capacitance between gate- and source-drain of a VLSI MOS device is derived. The expression takes into account finite polysilicon gate thickness, source-drain junction depth and different dielectric constants of silicon and oxide. A numerical procedure is also described to calculate the exact overlap capacitance with fringing, using the solution of Laplace's equation. A comparison is made to check the accuracy of the analytical expression. Good agreement is found. Experimently obtained gate-source capacitance curves are described. Overlap capacitance and fringing component values derived from these curves are also in good agreement to those predicted by the model.     

A comparison of MOS inversion layer charge and capacitance formulas

A test is made of a recent proposal by Lewyn and Meindl for approximation of MOS inversion layer charge and substrate capacitance. Included in the test are the charge sheet formula and a new formula derived here which includes the pinning of the depletion layer width in strong inversion. Comparison with numerical calculation shows the Lewyn-Meindl result for charge density is less accurate than the charge sheet result over the entire subthreshold region. Similar inaccuracy is expected in MOS current-voltage curves in the subthreshold region and near pinch-off. The new formula is better than the other two over the entire bias range. A comparison of dc and ac substrate capacitances shows the new result to be better than both of the other formulas. In inversion, however, the percent error in dc capacitance is large. This large percent error corresponds to a small absolute error because the dc capacitance goes to zero in strong inversion. The ac capacitance error in strong inversion is ∼5 percent because of neglect of the ac inversion layer redistribution. Percent error curves for all three formulas are presented as a function of band bending and reverse bias.     

A capacitance model for GaAs MESFETs

A capacitance model for a GaAs MESFET suitable for implementation in the circuit analysis program SPICE is presented. The model consists of nonlinear capacitances that are a function of two voltages. Such a model gives rise to ordinary nonlinear capacitances and transcapacitances. The placement of these elements in the Y matrix is shown. The empirical equations for the gate charge of a GaAs MESFET given provide an accurate SPICE model for the gate charge and capacitances of a MESFET. A comparison of measured capacitance values with the modeled values gives close enough agreement for circuit simulation purposes