KOH溶液中(11O)硅片腐蚀特性的研究

研究了在KOH溶液中(110)硅片的腐蚀特性,在保证(110)面的平整和{111}面的光滑的腐蚀实验条件下,利用(110)面和{111}面腐蚀选择比大,采用湿法腐蚀技术可以制作高深宽比结构的方式,在(110)硅片上设计制作出光开关用微反射镜.在腐蚀过程中光开关悬臂的凸角处产生了削角现象,利用表面硅原子悬挂键的分布特征对产生削角的原因作了合理解释,这为以后研究凸角补偿提供了理论依据.     

硅各向异性浅槽腐蚀实验研究

通过实验分析,对比了异丙醇(IPA)和超声波对Si(100)面在KOH溶液和四甲基氢氧化氨(TMAH)溶液中的浅槽腐蚀速率及其表面形态的影响。实验结果表明,IPA能降低TMAH溶液的腐蚀速率,但IPA在KOH溶液中腐蚀速率降低不明显;IPA加入到较高浓度的KOH溶液中,会在Si表面产生较大小丘,恶化了Si腐蚀表面的质量,但在TMAH溶液中加入一定量的IPA会改善腐蚀表面的质量;超声波能加快腐蚀速率并能改善Si腐蚀表面质量,但对于加入IPA的较高浓度KOH溶液,超声波未能消除Si腐蚀表面的小丘,另外,超声波还能减弱腐蚀过程中微尺寸沟槽的尺寸效应;在腐蚀条件和配比一定情况下,TMAH溶液的腐蚀质量比KOH溶液好。     

氢氧化钾和酸性溶液腐蚀硅片的比较

本文研究了KOH腐蚀法,它是代替酸腐蚀以去除硅片损伤的一种方法。业已发现,对硅片用户和生产者而言,KOH腐蚀均优于酸腐蚀。对硅片用户而言,KOH腐蚀使器件成品率更高,硅片更平整,背面形状更好,且避免了金属复盖层;对于硅片制造者而言,KOH腐蚀使下硅片成本更稳定更低,加工工艺更紧凑,加工环境要求更一般,加工温度更易于控制,腐蚀后硅片外形均匀性和一致性更好。作者确定了详细的腐蚀速率。     

测定硅各向异性腐蚀速率分布的新方法

介绍了一种测定硅各向异性腐蚀速率分布的新方法.硅各向异性腐蚀速率三维分布可由一系列晶面上的二维腐蚀速率分布表示.利用深反应离子刻蚀技术(DRIE)在{0mn}硅片上制作出侧壁垂直于硅片表面的矩形槽,测量槽宽度在腐蚀前后的变化,就可测定各{0mn}面上的二维腐蚀速率分布.将二维腐蚀速率分布组合在一起就得到了三维腐蚀速率分布.由于DRIE制作的垂直侧壁深度大,可耐受较长时间的各向异性腐蚀,所以只需使用一般的显微镜就能得到准确的结果.实验得到了40%KOH和25%TMAH中{n10}和{n11}晶面的腐蚀速率分布数据     

各向异性腐蚀制备纳米硅尖

采用KOH溶液各向异性腐蚀单晶硅的方法制备高纵横比的纳米硅尖,研究了腐蚀溶液的浓度、添加剂异丙醇(IPA)对硅尖形状的影响。设计了硅尖制作的工艺流程,制备了形状不同、纵横比值为0.52～2.1的硅尖,并结合晶面相交模型,提出了硅尖晶面的判别方法,讨论了实验中出现的{411}和{331}晶面族两种硅尖晶面类型,实验结果和理论分析相一致。通过分析腐蚀溶液的质量分数和添加剂对{411}、{331}晶面族腐蚀速度的影响,得到了制备高纵横比纳米硅尖的工艺参数。实验结果表明:当正方形掩模边缘沿<110>晶向时,在78℃、质量分数40的KOH溶液中腐蚀硅尖,再经980℃干氧氧化3h进行锐化削尖,可制备出纵横比大于2、曲率半径达纳米量级的硅尖阵列。     

KOH各向异性腐蚀中预处理对硅表面粗糙度的影响

通过实验研究表明:不同预处理方法对KOH腐蚀后硅片表面粗糙度的影响不同,分别用35℃的BOE(7:1氟化铵腐蚀液)、常温BOE、10:1 HF、50:1 HF含HF成分的腐蚀液对硅片进行预处理,再和未做预处理的硅片在同等条件下进行KOH腐蚀,实验结果发现预处理后硅片表面粗糙度比未做处理的硅片表面粗糙度增加约1 nm左右,即经过含HF成分的腐蚀液预处理后的硅片再进行KOH腐蚀,其表面粗糙度将变差.     

利用(110)硅片制作体硅微光开关的工艺研究

采用基于湿法腐蚀工艺的体硅微机械加工方法,利用(110 )硅片结晶学特性,通过光刻、反应离子刻蚀和湿法刻蚀等工艺,在硅片上同时制作出微光开关的微反射镜结构、悬臂梁结构、扭臂梁结构和光纤定位槽结构,器件的一致性好,制作工艺简单.利用扇形定位区域,精确地沿(110 )硅片的{ 111}面进行定向腐蚀,可使微反射镜镜面垂直度达到90±0 .3°,经测量表面粗糙度低于6 nm.     

交叉深沟槽硅外延的生长研究北大核心

随着先进半导体器件需求的不断提升,深沟槽硅外延已逐渐代替传统离子注入工艺成为器件开发的新方向,由于受晶向的影响,硅外延生长质量存在极大差异。通过<100>和<110>两种晶向硅片在交叉深沟槽中的外延生长,采用SEM和TEM分析了硅外延生长形貌和质量,运用TCAD模拟验证该结构下的外延生长机理,同时采用暗场扫描(DFI)和表面刻蚀方法检测硅片表面缺陷。结果表明硅晶向对交叉深沟槽外延的生长质量有重要影响,<100>硅片在交叉区域外延形成的{110}面和{111}面多,容易产生位错缺陷,而<110>硅片相比<100>硅片转向了45°,外延中形成的{110}面和{111}面减少了一半,从而外延质量改善明显。     

(110)硅基MEMS光开关光纤定位槽的设计

利用KOH溶液腐蚀在(110)硅片上制作2×2 MEMS光开关,微反射镜表面光滑且垂直度较好,其质量高于用同样方法在(100)硅片上制作的反射镜,但是却存在自对准V型槽难以实现的问题。依据(110)硅片的结晶学特点,设计并制作了夹角为38.94°的两个光纤定位槽:一个为U型槽,两侧面均为{111}面;另一个是呈锯齿状的光纤槽,它是由腐蚀出的平行四边形蚀坑串组成。介绍了锯齿状沟槽的实现原理,对平行四边形蚀坑尺寸进行了分析设计,并采用菱形凸角补偿结构实现凸角补偿。这两种光纤定位槽结构都能够很好地固定光纤,并实现了光纤的自对准,且制作方法简单。     

(110)硅基光纤定位槽的研究

利用(110)硅片在KOH溶液中各向异性腐蚀制作出两个互相垂直的光纤定位槽.由于在该方位腐蚀出的不标准的V型槽,难以对此精确设计来固定光纤.设计了利用KOH溶液定向腐蚀制作出的平行四边形蚀坑串,所形成的锯齿状沟槽结构来固定光纤.依据硅的各向异性腐蚀特性对平行四边形蚀坑尺寸进行了分析设计.由于腐蚀过程中锐角凸角和钝角凸角产生的削角面不一致,致使锯齿状沟槽精确固定光纤产生偏差,设计采用菱形凸角补偿结构进行完善,从而达到精确固定光纤的目的.     

Convex corners undercutting and rhombus compensation in KOH with and without IPA solution on (1 1 0) silicon

The present investigation introduces convex corners undercutting and results of rhombus compensation patterns in 40% aqueous KOH solution and in KOH saturated with isopropanol (IPA) solution. All experiments are carried out on (1 1 0) silicon at 70 °C. Undercuts take place on convex corners in both solutions. Moreover, the front etch planes governing undercut vary with solutions. Rhombus compensations are used to correct the undercut. Perfect acute corner without residue is obtained, and there are only some residue structures on both sides of obtuse convex corners in KOH with IPA solution, which are better results than those in pure aqueous KOH solution.     

恒温磁力搅拌下KOH刻蚀Si的研究

采用恒温磁力搅拌的方法,在KOH溶液中湿法刻蚀Si。在掩模层为SiO2时,研究了刻蚀速率随KOH浓度与温度的变化关系。结果表明:在110℃、30%的KOH溶液下,刻蚀Si(100)可以得到4.0μm/min的刻蚀速率,Si(100):SiO2的刻蚀速率比为550:1,Si(100):Si(111)的刻蚀速率比为90:1,而且可以得到光滑的刻蚀表面与形状。     

用于高灵敏度红外探测器的超薄硅膜的研制

超薄、平整的硅膜对于制作高灵敏度红外探测器是非常重要的。这种超薄硅膜的各向异性腐蚀技术，包括有机溶液EPW和无机溶液KoH及KoH IPA(异丙醇)。从腐蚀速率、腐蚀表面质量、腐蚀停特性、腐蚀边缘形貌及腐蚀工艺的角度分析比较了两种腐蚀系统，分别制作出了约1μm厚的平整超薄硅膜，并研究了不同掩膜材料在腐蚀液中的抗蚀性，为高灵敏度红外探测器的制作奠定了工艺基础。     

Etch characteristics of KOH, TMAH and dual doped TMAH for bulk micromachining of silicon

High precision bulk micromachining of silicon is a key process step to shape spatial structures for fabricating different type of microsensors and microactuators. A series of etching experiments have been carried out using KOH, TMAH and dual doped TMAH at different etchant concentrations and temperatures wherein silicon, silicon dioxide and aluminum etch rates together with <100> silicon surface morphology and <111>/<100> etch rate ratio have been investigated in each etchant. A comparative study of the etch rates and etched silicon surface roughness at different etching ambient is also presented.From the experimental studies, it is found that etch rates vary with variation of etching ambient. The concentrations that maximize silicon etch rate is 3% for TMAH and 22 wt.% for KOH. Aluminum etch rate is high in KOH and undoped TMAH but negligible in dual doped TMAH. Silicon dioxide etch rate is higher in KOH than in TMAH and dual doped TMAH solutions. The <111>/<100> etch rate ratio is highest in TMAH compared to the other two etchants whereas smoothest etched silicon surface is achieved using dual doped TMAH. The study reveals that dual doped TMAH solution is a very attractive CMOS compatible silicon etchant for commercial MEMS fabrication which has superior characteristics compared to other silicon etchants.     

Mechanism for convex corner undercutting of (110) silicon in KOH

The cantilever is fabricated on (110) silicon wafer by anisotropic wet etching method in KOH; the sidewall of cantilever is {111} plane, and it is vertical to the substrate. The convex corner is undercut, and the concave corner structure corresponds with the design. The mechanism of the convex corner undercutting is explained by the theory of covalent bond density.     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.