CMOS集成电路的功耗优化和低功耗设计技术

总结了当前已发展出的各个层次的CMOS低功耗设计技术和低功耗设计方法学的研究进展.重点介绍了时序电路的优化、异步设计、高层次电路设计和优化技术.     

双逻辑低功耗运算电路设计分析

主要研究双逻辑低功耗运算电路设计,采用了函数逻辑立方体表示技术,进行了双模式的逻辑侦测与划分,并进行了RM逻辑面积优化。双逻辑低功耗运算电路设计是当前集成电路设计研究工作的重点内容,对降低运算电路功耗效果显著。     

VLSI电路低功耗设计研究进展

介绍了低功耗设计最新的研究进展,从低功耗设计流程、功耗估计方法、功耗优化方法、功耗优化工具软件、低功耗测试等几个方面,对低功耗的研究进行了系统和科学的阐述,可为相关研究设计人员提供有益的参考.     

Android手机低功耗GPS导航软件设计与实现

随着智能手机功能日益丰富完善以及移动互联网的迅速发展,智能手机的功耗管理就显得越来越重要了.传统的关于功耗管理都是从显示屏、网络模块(GPRS/WiFi)和处理器等入手,文中通过优化GPS软件实现低功耗.通过阐述现在导航软件的工作原理并分析手机定位导航功耗情况,最后通过对比测试当前android系统4大主流导航软件功耗情况,并结合自己提出的低功耗编程以及软件运行流程,设计并实现了一款低功耗GPS导航软件,通过测试,验证了该软件的可行性以及低功耗特性.     

低功耗编译技术综述

功耗问题已经成为制约电子系统发展的重要因素.功耗是由硬件在运行软件时产生的,软件的数据存取和指令执行都会使硬件产生功耗.编译器可以通过适当的调度优化,改变软件在硬件上的运行轨迹,使得硬件执行某一个程序时的功耗变小.本文从如何对软件的功耗进行评估和如何实现低功耗的编译两大方面对低功耗编译的相关研究进行了广泛介绍,着重评述了专门的低功耗编译技术.最后对当前低功耗编译存在的问题做了分析,给出了对于低功耗编译新方向的预测.     

SoC设计中的低功耗技术

SoC越来越成为设计的主流趋势，而应用系统对低功耗无止境的需求，使得SoC低功耗设计技术变得日益重要。本文首先介绍了低功耗的基本概念，包括原理、优化技术等，着重介绍了面向SoC的系统级功耗优化技术，最后展望了SoC低功耗设计的一些发展方向。     

GNSS接收机基带处理电路低功耗设计综述

通过时GNSS接收机基带处理电路低功耗设计技术进行调研和总结,发现大部分技术可归属于两个层次：电路级优化技术和算法级优化技术。电路级优化技术主要包括低功耗的并行相关器的设计、多通道的时分复用、多普勒补偿后的信号下采样、低功耗累加器的使用等技术;算法级优化技术是指接收机的间歇工作方式（在不需要定位输出时,使接收机运行在低功耗模式）,主要通过接收机的高级电源管理系统、快速首次定位、重新捕获定位等技术实现。本文对这些方法进行了总结和对比,给出了两个层次优化技术的优缺点。     

SOC时代低功耗设计的研究与进展

在片上系统(SOC)时代,芯片内核的超高功耗密度以及移动应用市场对低功耗的无止境需求,使低功耗设计变得日益重要.文章全面系统地介绍了低功耗设计的相关内容,包括背景、原理和不同层次的功耗优化技术,着重介绍了面向SOC的系统级功耗优化技术.通过对已有研究成果按设计抽象层次和系统功能的分析,指出了其优化的全局性不够充分.提出了基于软硬件协同设计的系统功耗优化思路和设计流程,展望了SOC低功耗设计的发展方向.     

可编程逻辑器件低功耗技术

为降低可编程逻辑器件设计中的功耗问题,必须从系统的微结构入手,采用低功耗方案降低系统的功耗。首先介绍功耗产生的原因,并通过门控技术、器件选择、寄存器传输级的优化转换和门级低功耗优化技术4个方面,阐述了如何在逻辑层面上进行低功耗设计的基本思想和主要技术。     

AES算法的快速低功耗ASIC实现

论文根据一种改进的AES密码算法,提出了其低功耗ASIC设计与实现的方法。通过分析CMOS电路功耗产生原因,介绍了动态功耗管理、门控时钟和操作数隔离等低功耗设计方法,给出了该AES密码算法详细的低功耗实现方案。用Power Compiler做功耗分析后发现,优化后的功耗比优化前的功耗降低了43%,满足低功耗的要求。     

A high-efficiency low-voltage class-E PA for IoT applications in sub-1 GHz frequency range

We present and propose a complete and iterative integrated-circuit and electro-magnetic (EM) co-design methodology and procedure for a low-voltage sub-1 GHz class-E PA. The presented class-E PA consists of the on-chip power transistor, the on-chip gate driving circuits, the off-chip tunable LC load network and the off-chip LC ladder low pass filter. The design methodology includes an explicit design equation based circuit components values'' analysis and numerical derivation, output power targeted transistor size and low pass filter design, and power efficiency oriented design optimization. The proposed design procedure includes the power efficiency oriented LC network tuning, the detailed circuit/EM co-simulation plan on integrated circuit level, package level and PCB level to ensure an accurate simulation to measurement match and first pass design success. The proposed PA is targeted to achieve more than 15 dBm output power delivery and 40% power efficiency at 433 MHz frequency band with 1.5 V low voltage supply. The LC load network is designed to be off-chip for the purpose of easy tuning and optimization. The same circuit can be extended to all sub-1 GHz applications with the same tuning and optimization on the load network at different frequencies. The amplifier is implemented in 0.13 μm CMOS technology with a core area occupation of 400 μm by 300 μm. Measurement results showed that it provided power delivery of 16.42 dBm at antenna with efficiency of 40.6%. A harmonics suppression of 44 dBc is achieved, making it suitable for massive deployment of IoT devices.     

微波功率模块中高效率灯丝电源的设计

设计了可有效提高效率的小功率常规集成电源电路。在Pspice仿真的基础上，介绍了利用Magnetics Designer软件设计、优化高频变压器的方法，分析了合理选择开关管、输出整流管及RCD箝位电路参数的依据。通过实验测试，设计的灯丝电源在兼顾小型化的同时，满载效率达到92％。     

基于功能仿真的电路节点翻转信息提取

在基于功能仿真进行集成电路低功耗设计和研究中，往往需要通过获取电路节点的翻转信息来评估设计电路的功耗并指导相应的优化工作，论文采用PLI（progmmming Language Interface）编程来扩展仿真工具的功能直接获取设计电路中各个节点的工作状态，实现在仿真过程中节点翻转信息的提取，结果表明该方案不仅具有很大的灵活性而且对仿真效率的影响也最小。     

Techniques for power estimation and optimization at the logic level: A survey

We present a survey of state-of-the-art power estimation methods and optimization techniques targeting low power VLSI circuits. Estimation and optimizations at the circuit and logic levels are considered.     

Characteristics analysis and optimization design of a new ESD power clamp circuit

As CMOS technology scales down, the design of ESD protection circuits becomes more challenging. There are some disadvantages for the actual power clamp circuit. In this paper, an optimization ESD power clamp circuit is proposed. The new clamp circuit adopts the edge triggering True Single Phase Clocked Logic (TSPCL) D flip-flop to turn on and time delay, it has the advantage of dynamic transmission structure. By adding a leakage transistor of small size, the clamp circuit can turn off effectively. By changing the W/L ratio, the clamp can safely protect the gate of ESD power clamp devices from thermoelectric breakdown. The results show that the circuit can reduce the false triggering and power supply noise more effectively, it can be widely used in high-speed integrated circuits. The proposed structure has the advantages of low power and low cost, and can be used to the system-level ESD protection.     

Viterbi译码算法Soft Core IP的低功耗设计

介绍了Viterbi译码算法SoftCoreIP的一种低功耗实现方案,对其中的核心功能单元ACS(Adder_Compare_Select)提出了一种改进的设计结构,并介绍了电路时钟的优化技术及低功耗设计技术,经实验证明,确实达到了降低功耗、减小电路规模的设计目的。     

Precomputation-based sequential logic optimization for low power

We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. The primary optimization step is the synthesis of the precomputation logic, which computes the output values for a subset of input conditions. If the output values can be precomputed, the original logic circuit can be “turned off” in the next clock cycle and will have substantially reduced switching activity. The size of the precomputation logic determines the power dissipation reduction, area increase and delay increase relative to the original circuit. Given a logic-level sequential circuit, we present an automatic method of synthesizing precomputation logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay     

一种保护式脉冲电源变换器的设计

采用优化设计和模拟试验方法解决了ＳＨ０１２保护式脉冲电源变换器大功耗和小体积、两路输出差异大的矛盾,实现了保护功耗以及在工作温度范围内的高精度,提高了电路性能。采用二次集成工艺研制的脉宽调制型（ＰＷＭ）开关电源模块具有可靠性高、性能好、功耗低、体积小、重量轻的特点,并具有很好的保护功能,可用于各种高性能、小型化的电子仪器、仪表和设备。     

Technology mapping for low power in logic synthesis

Traditionally, three metrics have been used to evaluate the quality of logic circuits - size, speed and testability. Consequently, synthesis techniques have strived to optimize for one or more of these metrics, resulting in a large body of research in optimal logic synthesis. As a consequence of this research, we have today very powerful techniques for synthesis targeting area and testability; and to a lesser extent, circuit speed. The last couple of years have seen the addition of another dimension in the evaluation of circuit quality - its power requirements. Low-power circuits are emerging as an important application domain, and synthesis for low power is demanding attention.

The research presented in this paper addresses one aspect of low-power synthesis. It focuses on the problem of mapping a technology-independent circuit to a technology-specific one, using gates from a given library, with power as the optimization metric. We believe that the difficulty in obtaining accurate models of power at the technology-independent level makes it difficult to optimize for power at this level, and thus feel that the technology mapping step offers the most direct way of power optimization during logic synthesis.

Several issues in modeling and measuring circuit power, as well as algorithms for technology mapping for low power are presented here. Empirically it is observed that a significant variation in the power consumption is possible just by varying the choice of gates selected. In fact, our experiments over a large set of benchmark circuits show that compared to mapping for power, mapping for area or delay can lead to circuits that have significantly higher power consumption: up to 32% higher in case of mapping for area, and up to 153% higher in case of mapping for delay.     

基于TPS40055控制的新型同步BUCK电路设计

针对传统电源驱动电路启动慢,效率低,工作电流小,而目前光纤激光电源技术进入高集成化、高响应发展趋势的特点,提出了一种基于TPS40055控制的新型同步BUCK电路设计,可实现PWM及电流可调3路直流电源输出,各路电压分别为3.3V、5V、10 V,电流为0～11 A可调,能驱动不同型号大功率光纤激光器工作.从电路总体方案、工作原理、参数设计及优化等方面介绍此新型电源电路设计.结果证明,该设计能提供高效、可靠、稳定的激光器直流电源.