基于FPGA加密芯片的DPA实现与防御研究

差分功耗分析是破解AES密码算法最为有效的一种攻击技术,为了防范这种攻击技术本文基于FPGA搭建实验平台实现了对AES加密算法的DPA攻击,在此基础上通过掩码技术对AES加密算法进行优化与改进。通过实验证明改进后的AES算法能有效的防范DPA的攻击。     

AES密码算法的FPGA优化设计

主要介绍基于FPGA的AES算法优化设计.从AES加密算-法的介绍、Rijndael算法的描述、AES密码算法的优化设计、AES密码算法的FPGA实现、PC机与FPGA的通信设计等方面论述实现硬件加密的方法,手段、可行性和优越性;实现了基于FPGA技术的Rijndacl算法,并给出了相应的各种仿真波形和结果.     

分组密码处理器的可重构分簇式架构

该文在研究分组密码算法处理特征的基础上,提出了可重构分簇式分组密码处理器架构。在指令的控制下,数据通路可动态地重构为4个32bit簇,2个64bit簇和一个128bit簇,满足了分组密码算法数据处理所需的灵活性。基于分簇结构,提出了由指令显性地分隔电路结构的低功耗优化技术,采用此技术使得整体功耗降低了36.1%。设计并实现了5级流水线以及运算单元内流水结构,处理AES/DES/IDEA算法的速度分别达到了689.6Mbit/s, 400Mbit/s和416.7Mbit/s。     

一种小面积低功耗串行AES硬件加解密电路

通过分析AES算法的基本原理,对AES算法中的子模块SubBytes和Mixcolumns的硬件电路实现方法进行优化,提出一种新的key硬件电路实现方式,并在key的实现电路中采用低功耗设计.与目前的大多数实现电路相比,该电路可以有效减小芯片面积,降低电路功耗.采用串行AES加密/解密电路结构,经综合仿真后,芯片面积为8 054门,最高工作频率为77.4 MHz,对128位数据加密的速率为225 Mbps,解密速率达到183 Mbps,可满足目前大部分无线传感网络数据交换速率的需求.     

采用数据流模式提高乱序执行密码芯片的安全性

乱序执行是密码芯片设计中一种低冗余、低功耗的抵抗功耗分析攻击的方法.芯片安全性随着操作执行时刻不确定度的增加而提高.基于数据流模式的乱序执行AES加密集成电路采用动态数据流结构、对并发操作串行地随机服务,通过增加顺序无关操作的数量和成批处理令牌提高不确定度.其中采用了新的令牌暂存-匹配-发射结构完成令牌的同步和对随机执行的控制.实验芯片的所有操作均实现了不确定执行,可以抵抗样本数小于15000的相关功耗分析攻击,芯片功耗低于所知的其它抗功耗分析攻击AES芯片.     

一种抗DPA的AES的设计

为了防止智能卡在做加密运算时,旁路信息会通过功耗的变化而泄露,提出了一种抗差分功耗分析攻击的方法.首先研究了AES算法的加密规则,然后采用8位的处理器模拟智能卡,在智能卡上实现了对AES算法中的轮密钥加的差分功耗攻击.为了抵抗轮密钥加的差分功耗攻击,文中在算法级别上提出了一种掩码技术,其核心是用不同的随机量对密码运算过程中明文和密钥进行掩码,实验结果表明,该方法成功地抵抗了差分功耗攻击.     

AES密码分析的若干新进展

2001年11月,美国国家标准和技术研究所(NIST)确定Rijndael算法为新的数据加密标准-高级数据加密标准(AES).AES的密码分析是目前最受注目的一个研究问题.本综述介绍AES密码分析的一些新进展:包括积分密码分析,功耗分析和代数攻击等.作者就目前国内外的研究现状作了评述,并提出了AES密码分析的一些研究方向,希望能引起大家的重视.     

AES算法的密码分析与快速实现

高级加密标准(AES)确定分组密码Rijndael为其算法,取代厂泛使用了20多年的数据加密标准(DES),该算法将在各行业各部门获得广泛的应用.文章以DES为参照对象,阐述了Rijndael算法的设计特色,介绍了AES在密码分析方面国内外已有的一些理论分析成果,描述了AES算法采用软件和硬件的快速实现方案.     

多媒体SOC芯片的低功耗设计

从集成电路功耗原理出发,分析了CMOS电路功耗的来源,从集成电路设计的系统级、算法级、架构级、电路/门级以及工艺/器件级五个抽象层次出发,整理、总结了当前主要的低功耗设计方法,并在实际的移动多媒体处理应用SOC芯片设计中,平衡产品成本、设计复杂度、设计环境等多种因素,确定并应用了适合设计对象的低功耗设计方法的组合.通过对于样片功耗的测试分析,低功耗设计方法(组合)取得了预期的效果,实现了较低的动态功耗与很低的静态功耗.     

基于AES和RSA的XML加密方案及实现

本文在分析高级密码算法(AES)的基础上,将AES算法与目前国际上应用最广泛的公开密码算法(RSA)相结合,针对数据库数据提出一个基于AES和RSA的XML加密方案,并给出了其实现过程。     

Low-power design of decimation filters for a digital IF receiver

This paper presents low-power design techniques at the architectural level for design of decimation filters in a digital IF receiver for wide-area wireless data networks. A multimode decimation filter design implementing both Mobitex and Ardis networks is described. The power is reduced by a factor of 1422 and the area reduced by a factor of 7.85 compared to an optimized single-mode two-stage design. A new multistage decimation filter design tool is also presented, which compares alternative architectures on figures of merit which the low-power designer can map into technology-dependent area and power costs     

线列TDI型红外焦平面读出电路低功耗设计

摘要：基于对具有TDI功能的红外线列读出电路工作原理的分析,通过改变电路的工作电流及工作时间进行低功耗设计,最后分别对优化前后的读出电路进行直流仿真,仿真结果显示优化后读出电路功耗较原始电路降低了49.5%,验证了低功耗设计方案的可行性。     

A high-efficiency,low-noise power solution for a dual-channel GNSS RF receiver

A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented.The power solution involves a DC-DC buck converter and a followed low-dropout regulator(LDO).The pulsewidth -modulation(PWM) control method is adopted for better noise performance.An improved low-power highfrequency PWM control circuit is proposed,which halves the average quiescent current of the buck converter to 80μA by periodically shutting down the OTA.The size of the output stage has also been optimized to achieve high efficiency under a light load condition.In addition,a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current.Fabricated with commercial 180-nm CMOS technology,the DC-DC converter achieves a peak efficiency of 93.1%under a 2 MHz working frequency.The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB.     

一种产生正负倍压的电荷泵的优化设计

通过对传统的电荷泵进行结构改进和参数优化,得到了一种高效率、低功耗的电荷泵,并阐述了电荷泵的工作原理,分析了影响功耗和效率的因素。该电荷泵通过检测输出电压来控制泵压,大大降低了功耗;同时,再对开关管进行参数优化,进一步减小了功耗。最后,将该优化后的电荷泵应用到RS-232C串口通信电路中。通过仿真,对其性能进行了验证,并与传统电荷泵进行了比较。     

Short-circuit power driven gate sizing technique for reducing powerdissipation

One major challenge in low-power technology is how to reduce overall power dissipation of a given subsystem without impacting its performance. In this paper we present a technique that can be applied to the nonspeed-critical nets in a circuit in order to reduce overall power dissipation. This technique involves a study of short-circuit power dissipation as a function of input signal slews and output load conditions, to aid in making a judicious choice of drive strengths for various gates in a circuit. The resulting low-power solution does not degrade the original performance and yields a circuit which occupies less silicon area. The technique described here can be incorporated into any power optimization or synthesis tool. Lastly, we present the savings in power and area for a 32-b carry lookahead adder which was designed using the technique described here     

A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory

A 600-MHz single-chip multiprocessor, which includes two M32R 32-bit CPU cores , a 512-kB shared SRAM and an internal shared pipelined bus, was fabricated using a 0.15-/spl mu/m CMOS process for embedded systems. This multiprocessor is based on symmetric multiprocessing (SMP), and supports modified-exclusive-shared-invalid (MESI) cache coherency protocol. The multiprocessor inherits the advantages of previously reported single-chip multiprocessors, while its multiprocessor architecture is optimized for use as an embedded processor. The internal shared pipelined bus has a low latency and large bandwidth (4.8 GB/s). These features enhance the performance of the multiprocessor. In addition, the multiprocessor employs various low-power techniques. The multiprocessor dissipates 800 mW in a 1.5-V 600-MHz multiprocessor mode. Standby power dissipation is less than 1.5 mW at 1.5 V. Hence, the multiprocessor achieves higher performance and lower power consumption. This paper presents a single-chip multiprocessor architecture optimized for use as an embedded processor and its various low-power techniques.     

基于扰动观察法的MPPT控制优化策略

为了提高光伏发电系统的充电效率,系统控制器采用高性能低功耗的ATmega16单片机为核心,通过调节PWM波占空比实时改变Buck变换器的输出电压,采用扰动观察法的MPPT控制策略,实现对光伏发电系统最大功率点的跟踪。针对扰动观察法跟踪过程中可能由于快速扰动导致功率振荡和误判的问题,系统对MPPT算法进行优化,并通过友好的人机界面实时显示最大功率曲线图。测试结果表明,该方法能够保证光伏发电系统快速、稳定、精确地跟踪最大功率点,提高了充电效率。     

An InGaP-GaAs HBT MMIC smart power amplifier for W-CDMA mobile handsets

We demonstrate a new linearized monolithic microwave integrated circuit smart power amplifier of extraordinary high power-added efficiency (PAE), especially at the most probable transmission power of wide-band code-division multiple-access handsets. A PAE of 21% at 16 dBm of output power, which is the maximum bound of the most probable transmission power in IS-95 systems, was obtained, as well as 40% at 28 dBm, the required maximum output power, with a single-chip MMIC power amplifier. The power amplifier has been devised with two InGaP-GaAs heterojunction bipolar transistor amplifying chains parallel connected, each chain being optimized for a different P/sub 1dB/ (1-dB compression point) value: one for 16 dBm for the low-power mode, targeting the most probable transmission power, and the other for 28 dBm for the high-power mode. The high-power mode operation shows 40% of PAE and -30 dBc of adjacent channel leakage power ratio (ACLR) at the maximum output power of 28 dBm. The low-power mode operation exhibits -34 dBc of ACLR at 16 dBm with 14 mA of a quiescent current. This amplifier improves power usage efficiency and, consequently, the battery lifetime of the handset by a factor of three.     

New solutions for a low-cost power electronic building block formatrix converters

This paper analyzes some aspects of integrating the matrix converter (MC) bidirectional switches into a power module. The analysis produces two optimal topologies for a power module: one for low-power and another for medium/high-power MCs. A new power module topology for a low-power three-phase-to-three- phase MC is proposed. By using bootstrap circuits to feed the gate-drivers, the proposed configuration requires only three insulated power supplies for a complete MC. This proposal constitutes a solution recommended in the low-power range, where low cost and low volume are the main objectives. Furthermore, a configuration of a power electronic building block for MCs is proposed. This includes the commutation control logic and the overcurrent protection, provides safe operation, and eliminates the specific problem of operating the bidirectional switches     

KISS-16V2: a one-chip ASIC DSP solution for GSM

Outlines the requirements for the various digital signal processing functions of the pan-European digital mobile cellular telephone system in terms of computational power and RAM and ROM capacities, and describes a digital signal processor (DSP) solution which is able to integrate all of these digital baseband functions for a hand-held terminal onto one VLSI chip. The KISS-16V2 processor, a low-power CMOS 16-b DSP, is optimized for digital telecommunications, especially for Groupe Speciale Mobile (GSM). A power-down mode together with the capability of memory and multiplier standby operation make this DSP well suited for handheld devices. A design strategy based on the extensive use of cell compilers and synthesis tools reduces the design of further DSP derivations to a minimum.<>