SiC衬底X波段GaN MMIC的研究

使用国产6H-SiC衬底的GaN HEMT外延材料研制出高工作电压、高输出功率的AlGaN/GaN HEMT.利用ICCAP软件建立器件大信号模型,利用ADS软件仿真优化了双级GaN MMIC,研制出具有通孔结构的GaN MMIC芯片,连续波测试显示,频率为9.1～10.1 GHz时连续波输出功率大于10 W,带内增益大于12 dB,增益平坦度为±0.2 dB.该功率单片为第一个采用国产SiC村底的GaN MMIC.     

SiC ICP背面通孔刻蚀研究

介绍了利用ICP设备,使用SF6基气体对4H-SiC衬底进行背面通孔刻蚀的技术。研究了金属刻蚀掩模、刻蚀气体中O2含量的变化、反应室压力、RF功率和ICP功率等各种条件对刻蚀结果产生的影响,重点对刻蚀气体中O2含量和反应室压力两个条件进行了优化。通过对刻蚀结果的分析,得出了适合当前实际工艺的优化条件,实现了厚度为100μm、直径为70μm的SiC衬底GaN HEMT和单片电路的背面通孔刻蚀,刻蚀速率达700nm/min,SiC和金属刻蚀选择比达到60∶1。通过对工艺条件的优化,刻蚀出倾角为75°～90°的通孔。     

一种V波段高效率5W GaN功率放大器MMIC

基于0.13μm SiC基GaN高电子迁移率晶体管(HEMT)工艺,设计了一款V波段GaN功率放大器单片微波集成电路(MMIC)。该功率放大器MMIC采用三级放大拓扑结构以满足增益需求;使用高低阻抗微带传输线进行阻抗匹配,通过威尔金森功分器/合成器完成功率放大器的末端功率合成;通过对晶体管宽长比的设计与多胞晶体管的合成,实现了功率放大器的高功率稳定工作和高效率输出。经过测试,在59～61 GHz频率范围内,在占空比为20%、脉宽为100μs时,该功率放大器MMIC的饱和输出功率达到37 dBm以上,功率附加效率(PAE)大于21.1%,功率增益大于17 dB;连续波测试条件下输出功率大于36.8 dBm, PAE大于21%。该设计在输出功率和PAE上具有一定的优势。     

微波、毫米波GaN HEMT与MMIC的新进展(续)

3 MMIC技术 在芯片上由GaN HEMT有源器件和无源元件(如MIM电容、薄膜电阻和衬底上的通孔等)所组成的微波单片集成电路(MMIC)和GaN HEMT分立晶体管几乎同步发展,MMIC技术的发展使GaNHEMT器件的电路应用能减少体积和质量,适应高频率的需求和批量生产.目前4英寸(1英寸=2.54 cm)圆片级GaN MMIC加工线已经成熟,GaN MMIC的工作频率已覆盖微波到3 mm波段,GaN MMIC的性能向高效率、高功率、宽频带和多功能集成的方向发展.     

SiC衬底AlGaN/GaN HEMT的ICP通孔刻蚀

利用ICP对研制的SiC衬底上AlGaN/GaN HEMT刻蚀获得了深度为50μm的接地通孔.器件通孔制作前首先用机械研磨的方法将衬底减薄至50μm,在背面蒸发Ti/Ni并电镀Ni至3μm作为刻蚀阻挡层;之后利用SF6/O2混合气体的电感耦合等离子体对SiC衬底进行了刻蚀;最后将Cl2和BCl3混合气体的ICP刻蚀技术运用于AlGaN/GaN外延材料的刻蚀,完成了深度为50μm的AlGaN/GaN HEMT通孔制作,通孔侧壁具有一定的斜率,适合良好的金属覆盖以形成器件正面和背面的连接.这一技术非常适合AlGaN/GaN HEMT及其单片集成电路的研制.     

SiC衬底AlGaN/GaN HEMT的ICP通孔刻蚀

利用ICP对研制的SiC衬底上AlGaN/GaN HEMT刻蚀获得了深度为50μm的接地通孔. 器件通孔制作前首先用机械研磨的方法将衬底减薄至50μm,在背面蒸发Ti/Ni并电镀Ni至3μm作为刻蚀阻挡层;之后利用SF6/O2混合气体的电感耦合等离子体对SiC衬底进行了刻蚀;最后将Cl2和BCl3混合气体的ICP刻蚀技术运用于AlGaN/GaN外延材料的刻蚀,完成了深度为50μm的AlGaN/GaN HEMT通孔制作,通孔侧壁具有一定的斜率,适合良好的金属覆盖以形成器件正面和背面的连接. 这一技术非常适合AlGaN/GaN HEMT及其单片集成电路的研制.     

0.5μm AlGaN/GaN HEMT及其应用

报道了采用I线步进光刻实现的76.2 mm SiC衬底0.5μm GaN HEMT.器件正面工艺光刻均采用了I线步进光刻来实现,背面用通孔接地.栅脚介质刻蚀采用一种优化的低损伤RIE刻蚀方法实现了60°左右的侧壁倾斜角,降低了栅脚附近峰值电场强度,提高器件性能和可靠性.研制的GaN HEMT器件fT为15 GHz,fm...     

高效率X波段GaN MMIC功率放大器的研制

突破了GaN MMIC功率放大器的设计、制造、测试等关键技术,研制成功X波段GaN MMIC功率放大器。设计及优化了电路拓扑结构及电路参数,放大器芯片采用了国产外延材料及标准芯片制作工艺。单片功率放大器包含两级放大电路,采用了功率分配及合成匹配电路,输入输出阻抗均为50Ω。制作了微波测试载体及夹具,最终实现了X波段GaN MMIC功率放大器微波参数测试。在8.7～10.9 GHz频率范围内,该功率放大器输出功率大于16 W,功率增益大于14 dB,增益波动小于0.4 dB,输入驻波比小于2∶1,功率附加效率大于40%,带内效率最高达52%。     

14W X波段AlGaN/GaN HEMT功率MMIC

报道了研制的SiC衬底AIGaN/GaN HEMT微带结构微波功率MMIC,芯片工艺采用凹槽栅场板结构提高AlGaN/GaNHEMTs的微波功率特性.S参数测试结果表明AlGaN/GaN HEMTs的频率特性随器件的工作电压变化显著.研制的该2级功率MMIC在9～11GHz带内30V工作,输出功率大于10W,功率增益大于12dB,带内峰值输出功率达到14.7W,功率增益为13.7dB,功率附加效率为23%,该芯片尺寸仅为2.0mm×1.1mm.与已发表的X波段AlGaN/GaN HEMT功率MMIC研制结果相比,本项工作在单位毫米栅宽输出功率和芯片单位面积输出功率方面具有优势.     

14W X波段AlGaN/GaN HEMT功率MMIC

报道了研制的SiC衬底AIGaN/GaN HEMT微带结构微波功率MMIC,芯片工艺采用凹槽栅场板结构提高AlGaN/GaNHEMTs的微波功率特性.S参数测试结果表明AlGaN/GaN HEMTs的频率特性随器件的工作电压变化显著.研制的该2级功率MMIC在9～11GHz带内30V工作,输出功率大于10W,功率增益大于12dB,带内峰值输出功率达到14.7W,功率增益为13.7dB,功率附加效率为23%,该芯片尺寸仅为2.0mm×1.1mm.与已发表的X波段AlGaN/GaN HEMT功率MMIC研制结果相比,本项工作在单位毫米栅宽输出功率和芯片单位面积输出功率方面具有优势.     

Development of three-dimensional chip stacking technology using a clamped through-silicon via interconnection

This study aims at developing an advanced clamped through-silicon via (C-TSV) interconnection technology for three-dimensional (3D) chip-to-chip or chip-to-wafer packaging. The special features of the C-TSV technology include (1) the proposal of metal caps on the pads of the chip to form a nearly symmetric double-side-metal-cap structure that firmly clamps the vias on the chip, (2) the employment of a temporary conductive layer on the active side of the wafer as a seed metal layer during the electro-plating of metal caps, and (3) the introduction of a “via first redistribution” (VFR) concept in the C-TSV process for heterogeneous 3D integration and maximal performance. Basically, the metal caps can act as a bonding layer for 3D chip stacking and also a protection stopper for backside drilling. The blind vias are created using a proven low-cost laser drilling process through the wafer backside with a laminated insulation layer on the via-hole wall. Unlike the typical TSV process, the present technology has no need to carry out the seed layer deposition and photo processes to facilitate the via-hole filling with metal through electro-plating, thus being more cost-effective. Besides, because of the structural symmetry and also the tightly-clamped via structure, it can potentially yield better bonding reliability for stacked chip bonding. To demonstrate the effectiveness of the C-TSV structure for wafer-level 3D integration, feasibility study of the implementation of the novel process and mechanics comparisons of these two 3D chip stacking structures under thermal loading through finite element (FE) stress simulation are made. At last, both the thermal humidity (TH) test of 85 °C/85%RH and the 288 °C solder dipping test are carried out to demonstrate the interconnect reliability and the interface quality of the 3D interconnect technology.     

Flexible Chip-on-Flex (COF) and embedded Chip-in-Flex (CIF) packages by applying wafer level package (WLP) technology using anisotropic conductive films (ACFs)

Due to increasing demand for higher performance, greater flexibility, smaller size, and lighter weight in electronic devices, extensive studies on flexible electronic packages have been carried out. However, there has been little research on flexible packages by wafer level package (WLP) technology using anisotropic conductive films (ACFs) and flex substrates, an innovative packaging technology that requires fewer process steps and lower process temperature, and also provides flexible packages. This study demonstrated and evaluated the reliability of flexible packages that consisted of a flexible Chip-on-Flex (COF) assembly and embedded Chip-in-Flex (CIF) packages by applying a WLP process.The WLP process was successfully performed for the cases of void-free ACF lamination on a 50 μm thin wafer, wafer dicing without ACF delamination, and a flip-chip assembly which showed stable bump contact resistances. The fabricated COF assembly was more flexible than the conventional COF whose chip thickness is about 700 μm. To evaluate the flexibility of the COF assembly, a static bending test was performed under different bending radiuses: 35 mm, 30 mm, 25 mm, and 20 mm. Adopting optimized bonding processes of COF assembly and Flex-on-Flex (FOF) assembly, CIF packages were then successfully fabricated. The reliability of the CIF packages was evaluated via a high temperature/humidity test (85 °C/85% RH) and high temperature storage test (HTST). From the reliability test results, the CIF packages showed excellent 85 °C/85% RH reliability. Furthermore, guideline of ACF material property was suggested by Finite Element Analysis (FEA) for better HTST reliability.     

基于76.2 mm圆片工艺的GaN HEMT可靠性评估

报道了利用76.2 mm圆片工艺实现了SiC衬底GaN HEMT微波功率管的研制,并对其进行了多项试验以评估其可靠性.器件工艺中通过引入难熔金属作器件肖特基势垒,有效提高了GaN HEMT器件肖特基势垒的热稳定性,经过500℃高温处理30 s后器件肖特基特性依然保持稳定.随后的高温工作寿命试验表明,该GaNHEMT能够...     

数字化红外探测器的读出电路晶圆测试系统研究

数字化红外探测器的读出电路晶圆测试是评价晶圆的重要环节。在现有探针台测试设备的基础上，研制了一块电路板装置。它既可驱动晶圆工作，也可将不同形式的数字化输出信号转换为统一的数字图像传输格式,而且测试过程中可对电路板参数进行设置。首先对红外探测器读出晶圆测试系统进行了介绍，然后对研制的测试电路板装置进行了原理分析。最后将此电路板进行硬件实现，并编写了内部测试程序，完成了功能验证。对差分输出和单路输出两种形式的晶圆进行了测试，其结果与晶圆低温下的测试结果一致，数据准确可靠。此外电路装置有100个输入接口，可重复编程，支持24bit及以下输出位宽数字化晶圆的测试，使测试系统具有更高的兼容性和灵活性。     

Hybrid dry-wet chemical etching process for via holes for galliumarsenide MMIC manufacturing

Through the wafer via-hole connections for monolithic microwave integrated circuits (MMIC) manufacturing have been developed by combining reactive ion etching (RIE) and wet chemical spray etching processes for 100-μm-thick gallium arsenide wafers. The dry process is based on the use of SiCl₄-BCl₃-Cl₂ and BCl₃-Cl₂ gas mixtures at room temperature is a reactive ion etcher. The etching parameters are optimized for anisotropic etching, initially, followed by slightly isotropic etching. To remove the residual `lip' and surface roughness, following reactive ion etching, a dynamic wet chemical spray etching based on H₃PO₄-H₂O₂-H₂O at 45°C is used. The combined dry-wet etching approach is used to fabricate <120-μm diameter via-holes in 100-μm-thick GaAs substrates with a wider process latitude. With this process, the authors have achieved >95 percent yield across 3-in wafers. Metallized via-hole contacts to power FET chips show a contact resistance <20 mΩ per via for 5-μ-thick selective gold plating     

化学机械抛光对铜互连器件的影响及失效分析

探讨了Cu化学机械抛光(CMP)工艺引起Cu互连器件失效的原因以及对可靠性的影响,对Cu CMP工艺缺陷导致器件失效的案例进行分析.由于CMP的技术特点,不可避免地会产生一些工艺缺陷和工艺误差,从而引起器件失效.必须根据标准要求,出厂或封装前对圆片进行芯片功能参数测试和严格的镜检,以便在封装前剔除存在潜在工艺缺陷的芯片,达到既定可靠性要求.     

SiC MESFET高温工作寿命研究

对在76.2 mm 4H-SiC半绝缘衬底上研制的SiC MESFET进行了高温工作寿命试验,试验结果表明采用Au/Ti/欧姆接触结构的器件在结温275℃条件下工作500h后,饱和电流下降幅度超过了29％,器件均发生失效.分析表明器件失效的主要原因是Ti层扩散使欧姆接触性能下降.改进工艺采用WTi作为扩散阻挡层后,扩散...     

多层UV-LIGA惯性开关温度可靠性评估研究

为了评估采用UV-LIGA技术制作的多层MEMS惯性开关的温度可靠性,进行了可靠性强化试验。介绍了开关的结构特征、工作原理和制作工艺。建立了试验系统,对开关进行温度循环和振动冲击试验。利用扫描电子显微镜观察开关失效模式,并利用公式进行热应力分析。试验结果表明,开关主要失效模式为位错和分层。开关热应力分析结果表明,种子层为开关薄弱位置。结合可靠性强化实验和热应力分析结果,从结构设计和制作工艺角度提出了可靠性强化方法。该研究为应用于极限温度环境下的多层UV-LIGA惯性器件的设计与制作提供了试验依据。     

An in-line process monitoring method using electron beam induced substrate current

In-line process monitoring technology plays a vital role in accelerating yield ramps and quickly identifying and resolving yield excursions in the system on a chip era. We have developed an in-line process monitoring method that uses electron beam induced substrate current. It is especially suitable for deep contacts and via holes. This method makes it possible to monitor non-destructive contacts and the via-hole formation process with a hole-bottom nm-order SiO₂ film thickness measurement and a hole-bottom diameter measurement. Moreover, it allows us to evaluate etching-process variation over an 8-inch wafer in less than 20 min. The results can be used for in-line device sorting as well as for decisions regarding the timing of etching machine maintenance.     

太阳电池用Si片切割过程中浆料作用研究

Si片生产技术及工艺的进步使得太阳电池用Si片的切片厚度不断降低,而超薄的太阳电池用Si片必须通过多线切割机进行切割.基于Si片切割过程中砂浆性能对Si片表面质量、Si片成片率和切割线寿命的影响,分析了多线切割机中切削液的性能,并采用不同工艺参数多次进行试验,总结出了砂浆对太阳电池用Si片切割状态的影响因素.通过分析,得出了改善砂浆性能来提高多线切割机切片性能并获得更高的Si晶片表面质量的方法.