高精度SAR ADC电容阵列设计及校准算法

在高精度逐次逼近寄存器模数转换器(SAR ADC)中,电容阵列是SAR ADC的核心之一。电容阵列中的电容失配问题是导致转换精度降低的一个重要原因。为了尽可能改善这一问题,设计了一种6+6+6分段电容阵列,并且基于这种阵列设计了权重迭代算法的前台数字校准。该方法不需要额外的电容阵列,利用自身的电容阵列与比较器量化出电容失配,计算出每一位输出码的权重校准系数,用来对正常量化出的输出码进行编码,实现校准功能。仿真结果表明,引入电容失配的18 bit SAR ADC经过该算法校准后,信噪比(SNR)从77.6 dB提升到107.6 dB,无杂散动态范围(SFDR)从89.8 dB提升到125.6 dB,有效位数(ENOB)从12.54 bit提升到17.54 bit。在SMIC 0.18μm工艺下,该校准算法对高精度SAR ADC的动态性能具有较大提升。     

一种用于14 bit SAR ADC的DAC设计

本文设计了用于14bit逐次逼近型模数转换器（SAR ADC）的DAC电路。针对该DAC,介绍一种全差分分段电容阵列结构以缩小DAC的版图面积;高二位权电容采用热码控制,用以改善高位电容在转换时跳变的尖峰以及DAC的单调性;对电容阵列采用数字校准技术,减小电容阵列存在的失配,以提高SAR ADC精度。校准前,SAR ADC的INL达到10LSB,DNL达到4LSB;与校准前相比,校准后,INL〈0.5LSB,DNL〈0.6LSB。仿真结果表明,本DAC设计极大改善SAR ADC的性能,已达到设计要求。     

用于BAN的自校准SAR ADC设计

基于SMIC 0.18 μm CMOS混合信号工艺,设计了一种适用于体局域网(BAN)的自校准逐次逼近型模数转换器(SAR ADC)。基于BAN系统的特点,设计的SAR ADC采用阻容混合型主数模转换器(DAC)及电容型校准DAC等结构。采用误差自校准技术来校准SAR ADC的阻容混合型主DAC的高5位电容失配误差,有效降低了SAR ADC非线性误差。仿真结果表明,自校准SAR ADC获得了±0.3 LSB微分非线性、±1 LSB积分非线性、82.2 dB信噪比等性能特性。设计的SAR ADC具有良好的性能,适合于BAN系统。     

基于亚稳态检测的SAR ADC电容失配校准算法

随着工艺进程的不断推进,逐次逼近型模数转换器(SAR ADC)的电容失配对整体电路的速度和精度影响越来越大。针对SAR ADC中电容失配的问题,提出一种基于亚稳态检测的SAR ADC电容失配校准算法,在不增加模拟电路时序复杂度的情况下,有效地解决了电容失配导致的SAR ADC精度不足问题。将该算法运用于12 bit 150 MS/s SAR ADC中,模拟结果表明,有效位数(Enob)可以达到11.93 bit,无杂散动态范围(SFDR)达到92.66 dB。     

一种可校正的12位C2C电容阵列混合结构SAR ADC

提出了一种可校正的12位C2C电容阵列混合结构逐次逼近型模数转换器(SAR ADC),其数模转换器(DAC)由低6位分裂式C2C DAC阵列与高6位二进制DAC阵列构成。提出的混合结构DAC既解决了中高精度二进制SAR ADC中总电容过大的问题,又避免了分段式二进制DAC分数值桥接电容无法与单位电容形成匹配的问题。该结构能显著降低整个ADC的动态功耗。此外,将高位终端电容和低2~6位量化电容拆分成相等的两个电容,引入冗余量,使得该ADC的电容权重可以被校准,降低了电容失配以及寄生电容的影响。最后,为了避免电容上极板复位信号因电容阵列容值大而导致的延时偏大问题,采用高6位DAC采样的方式,并在高6位DAC中引入单位电容大小的终端电容,弥补了参考电压区间不完整的缺陷。仿真结果显示,在1.5 V电压下,该ADC总体功耗仅为111.84 μW,ENOB为12.49位,SFDR为91.46 dB,SNDR为76.97 dB。     

一种基于扰动的SAR ADC数字校准算法

为了减少分段式电容阵列ADC中分段电容引起的电容失配效应对转换精度的影响,采用最小均方根(LMS)迭代方法,实现了一种基于扰动的逐次逼近型(SAR)ADC数字前台校准算法。对同一个模拟输入信号先后加入作为扰动的模拟失调电压+Δd和-Δd,依次进行量化。使用LMS对两次量化结果进行加权迭代,得到最佳权重,实现了对ADC的校准。针对电容失配效应、寄生电容效应的影响,搭建了14位SAR ADC数模混合仿真验证系统。仿真结果表明,该校准算法将系统的无杂散动态范围(SFDR)从62.6 dB提升到87.7 dB。     

基于16位SAR模数转换器的误差校准方法

为了实现较高精度(16位及更高)的逐次逼近(SAR)ADC,提出了一种误差自动校准技术。考虑到芯片面积、功耗和精度的折中,采用了电荷再分配分段电容DAC结构,并采用准差分输入方式提高ADC的信噪比。为了消除电容失配引入的误差,提出了一种误差自动校准算法,利用误差校准DAC阵列对电容失配误差进行量化并存储在RAM中,在AD转换过程中实现误差消除。     

一种用于16位流水线ADC的多比特子DAC电容失配校准方法

多比特子DAC的电容失配误差在流水线AIX:输出中引入非线性误差,不仅严重降低AEK、转换精腰.而且通常的校准技术无法对非线性误差进行校准.针对这种情况,本文提出了一种用于16位流水线ADC的多比特子DAC电容失配校准方法.该设计误差提取方案在流片后测试得到电容失配误差.进而计算不同输入情况下电容失配导致的MDAC输出误差,根据后级的误差补偿电路将误差转换为卡乏准码并存储在芯片中,对电容失配导致的流水级输出误差进行校准.仿真结果表明.卡《准后信噪失真比SINAD为93.34 dB.无杂散动态范围SFDR为117.86 dB,有效精度EN()B从12.63 bit提高到15.26 bit.     

一种应用于高精度SAR ADC校准的剪枝神经网络算法

介绍了一种基于剪枝神经网络的后台校准算法,能够对高精度单通道SAR ADC的电容失配、偏移、增益等多个非理想因素同时进行校准,有效提高SAR ADC的精度。本算法不仅可以达到全连接神经网络校准效果,而且同时对贡献小的权重进行剔除,降低了校准电路的资源消耗,加快了神经网络校准算法速度。仿真结果表明,信号频率接近奈奎斯特频率的情况下,对16 bit 5 MS/s的 SAR ADC进行校准,校准后ADC的有效位数从7.4 bit提高到15.6 bit,无杂散动态范围从46.8 dB提高到126.2 dB。     

用于SAR ADC的低开销电容开关时序设计

逐次逼近型模数转换器(SAR ADC)中,数模转换器单元(DAC)是能耗和面积的主要来源之一。为了降低DAC的能耗和面积,提出了一种低开销电容开关时序,以此设计了DAC的结构,并进行逻辑实现。相比于传统型开关时序,该电容开关时序使得DAC的能耗降低了98.45%,面积减小了87.5%。基于该电容开关时序实现了一种12位SAR ADC。仿真结果表明,在1.2 V电源电压、100 kS/s采样速率的条件下,该ADC功耗为12.5 μW,有效位数为11.2位,无杂散动态范围为75.6 dB。     

一种带二进制校正的10位100 MS/s SAR ADC

基于SMIC 65 nm CMOS工艺,设计了一种带二进制校正的10位100 MS/s逐次逼近型模数转换器(SAR ADC),主要由自举开关、低噪声动态比较器、电容型数模转换器(C-DAC)、异步SAR逻辑以及数字纠错电路组成。电容型数模转换器采用带2位补偿电容的拆分单调电容转换方案,通过增加2位补偿电容,克服了电容型数模转换器在短时间内建立不稳定和动态比较器失调电压大的问题,使SAR ADC的性能更加稳定。数字纠错电路将每次转换输出的12位冗余码转换成10位的二进制码。使用Spectre进行前仿真验证,使用Virtuoso进行版图设计,后仿真结果表明,当电源电压为1.2 V、采样率为100 MS/s、输入信号为49.903 MHz时,该ADC的SNDR达到58.1 dB,而功耗仅为1.3 mW。     

A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS

A 10-bit 300-MS/s asynchronous SAR ADC in 65 nm CMOS is presented in this paper. To achieve low power, binary-weighed capacitive DAC is employed without any digital correction or calibration. Consequently, settling time for the capacitive DAC would be a dominant limiting factor for the ADC operating speed. A novel architecture is proposed to optimize the settling time for the capacitive DAC, which depends merely on the on-resistance of switches and the capacitance of unit capacitor and irrelevant to the resolution. Therefore, high-speed high-resolution SAR ADC is possible. What is deserved to highlight is that the architecture improves the ADC performance at a fraction of the cost, with only some capacitors and control logic added. Post-layout simulation has been made for the SAR ADC. At a 1.2-V supply voltage and a sampling rate of 300 MS/s, it consumes 1.27 mW and achieves an SNDR of 60 dB, an SFDR of 67.5 dB, with the Nyquist input. The SAR ADC occupies a core area of 450×380 μm².     

基于分段电容阵列的改进型逐次逼近型ADC

为缩短高速模数转换器(ADC)中高位(MSB)电容建立时间以及减小功耗,提出了一种基于分段式电容阵列的改进型逐次逼近型(SAR)ADC结构,通过翻转小电容阵列代替翻转大电容阵列以产生高位数字码,并利用180 nm CMOS工艺实现和验证了此ADC结构。该结构一方面可以缩短产生高位数码字过程中的转换时间,提高量化速度;另一方面其可以延长大电容的稳定时间,减小参考电压的负载。通过缩小比较器输入对管的面积以减小寄生电容带来的误差,提升高位数字码的准确度。同时,利用一次性校准技术减小比较器的失配电压。最终,采用180 nm CMOS工艺实现该10 bit SAR ADC,以验证该改进型结构。结果表明,在1.8 V电源电压、780μW功耗、有电路噪声和电容失配情况下,该改进型SAR ADC得到了58.0 dB的信噪失真比(SNDR)。     

Design considerations of calibration DAC in self-calibrated SAR A/D converters

A capacitive calibration digital-to-analog converter (CDAC) is commonly used to reduce the mismatch-induced linearity errors for successive approximation register (SAR) analog-to-digital converters (ADC) employing capacitor arrays. There are complicated design considerations in determining the number of bits, the unit capacitor value and even the parasitic capacitors of the CDAC, as these factors affect or are determined by the achievable ADC resolution, the main DAC's capacitance, and the main DAC unit capacitance value, etc. This paper is the first to present a systematic analysis on these relationships. The analysis is validated by behavioral and circuit simulation results.     

An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration

This paper presents a self-testing and calibration technique for the embedded successive approximation register (SAR) analog-to-digital converter (ADC) in system-on-chip (SoC) designs. We first proposed a low cost design-for-test (DfT) technique that estimates the SAR ADC performance before and after calibration by characterizing its digital-to-analog converter (DAC) capacitor weights (bit weights). Utilizing major carrier transition (MCT) testing, the required analog measurement range is only about 1 LSB; this significantly reduces test circuitry complexity. Then, we develop a fully-digital calibration technique that utilizes the extracted bit weights to correct the non-ideal I/O behavior induced by capacitor mismatch. Simulation results show that (1) the proposed testing technique achieves very high test accuracy even in the presence of large noise, and (2) the proposed calibration technique effectively improves both static and dynamic performances of the SAR ADC.     

低DNL的SAR型模数转换器的设计

保证DAC中元器件的精度、减小DNL误差是提高SAR ADC性能的关键。通过对SAR ADC内部DAC的结构进行综合分析,针对传统的C-R混合式结构中的集总电容阵列进行了优化设计。电容阵列由相同的非集总的单位电容组成,并通过数字逻辑的控制来实现对单位电容连接点的选择。验证结果证明设计有效,ENOB、SFDR和SINAD等参数都得到明显的提高,保证了SARADC的单调性,实现了低DNL的SAR型模数转换器的设计。     

High-linear,energy-efficient and area-efficient switching algorithm for high-speed SAR ADCs

Decreasing the size of DAC capacitors is a solution to achieve high-speed and low-power successive-approximation register analog-to-digital converters (SAR ADCs). But decreasing the size of capacitors directly effects the linearity performance of converter. In this paper, the effect of capacitor mismatch on linearity performance of charge redistribution SAR ADCs is studied. According to the achieved results from this investigation, a new tri-level switching algorithm is proposed to reduce the matching requirement for capacitors in SAR ADCs. The integral non-linearity (INL) and the differential non-linearity (DNL) of the proposed scheme are reduced by factor of two over the conventional SAR ADC which is the lowest compared to the previous schemes. In addition, the switching energy of the proposed scheme is reduced by 98.02% as compared with the conventional architecture which is the most energy-efficient algorithms in comparison with the previous algorithms, too. To evaluate the proposed method an 8-bit 50 MS/s SAR ADC is designed in 0.18 um CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 25-MHz input with 48.16 dB SNDR while consuming about 589 μW from a 1.2-V supply.     

A self-calibration method for capacitance mismatch in SAR ADC with split-capacitor DAC

A self-calibration method to calibrate the nonlinearity due to capacitance mismatch in successive approximation register (SAR) analog-to-digital converter (ADC) is presented. It focuses on calibrating the most significant bit (MSB) array in the split-capacitor main DAC (split-MDAC) by using a calibration DAC (CDAC) that contains multiple sub-CDACs. Every bit in MSB array has its corresponding sub-CDAC in CDAC, which enhances the calibration efficiency. To verify the calibration method, a 14 bit, 500 kS/s SAR ADC is implemented, and it is manufactured in 0.35 μm 2P4M CMOS process. The measured results show that the proposed calibration method can assist this SAR ADC to achieve better static and dynamic performance, and its ENOB is improved from 9 bit to 11.98 bit at Nyquist input frequency.