Simplified Modeling of a Multipole Amplifier Using All-Pass Network Functions

This paper presents a system model for the representation of amplifiers that cannot be accurately characterized by a classical two pole transfer function. The effects of higher order poles are modeled by an all-pass function added to the conventional two pole model. The accuracy of the model is demonstrated by comparing the results for a typical CMOS amplifier to those obtained from device level simulations using SPICE. This model can be easily implemented in a standard simulator and is shown to achieve fast simulation time. This model is expected to have application in system level modelling of mixed-signal circuits using conventional SPICE simulators.Yihong Dai received his B.S. and M.Eng. degrees in Electrical Engineering from Shanghai JiaoTong University, Shanghai, China in 1993 and 1996, respectively. From 1996 to 1998, he enjoyed his industrial experiences in Shanghai with semiconductor companies like Shanghai Nortel Semiconductor and Motorola Electronics (China) Shanghai Branch. Since 1998, he has been a research assistant at the Analog and Mixed-signal Laboratory of the Electrical Engineering Department of Brigham Young University working toward his Ph.D. During the summer of 1999, he was with AMI semiconductor Utah Research and Design Center where he developed a threshold voltage based CMOS voltage reference architecture. In the summer of 2001, he was with Ultra Design where he designed a reference amplifier for high speed digital-to-analog converters. His research interest includes voltage reference, reference amplifier and high speed data converters in both CMOS and GaAs processes.Donald T. Comer received the B.S, M.S., and Ph.D. degrees from San Jose State University, the University of California (Berkeley), and the University of Santa Clara, respectively, all in electrical engineering. He began teaching at San Jose State University in 1961 and mixed his teaching and industrial work until he left San Jose State University in 1979. He has worked for California Technical Industries, IBM Corp., Mobility Systems, Precision Monolithics, Storage Technology Corp., and Analog Devices during his career. He founded the AMI Utah Research and Design Center in 1998 that specializes in MOS design. In 2002, Dr. Comer founded Ultra Design, a design center that specializes in high-frequency heterojunction circuit designs. He holds fifteen patents and has published over 50 articles dealing with solid-state and integrated circuits. He has published five textbooks in the field of large-signal and integrated circuits. He formerly held the Quentin Berg Chair at Penn State Harrisburg from 1990 to 1995. He is now a professor of electrical and computer engineering at Brigham Young University where he held the Endowed Chair of Engineering from 1995 to 1998.David J. Comer received the B.S., M.S., and Ph.D. degrees from San Jose State University, the University of California (Berkeley), and Washington State University, respectively, all in electrical engineering. He has worked for IBM Corp., Pacific Electromagnetics, Lawrence Livermore Laboratories, and Intel Corporation. He began his teaching career at the University of Idaho and has taught at the University of Calgary and California State University, Chico. He is presently a professor of electrical and computer engineering at Brigham Young University. He served as Chairman of the Division (Dean) of Engineering at CSU, Chico and as Department Chair at BYU.While at CSU, Chico, Dr. Comer served on the statewide Engineering Liaison Committee and served as Chair of the Council of California State University Deans of Engineering.Dr. Comer has published twelve textbooks and over 60 articles in the field of circuit design. He has contributed sections to the Encyclopedia of Physical Science and Technology and holds seven patents. He was given the Professional Achievement Award at CSU, Chico and was named the Outstanding Teacher of Engineering at BYU. He has also held the College of Engineering Research Chair at Brigham Young University.Darren Korth received the B.S. and M.S. degrees in electrical engineering at Brigham Young University, Provo, Utah in 1999. He is currently pursuing a Ph.D. in electrical engineering. He served as an instructor for the Department of Electrical and Computer Engineering at Brigham Young University from 2000 to 2002. From 2001 to 2003, he also worked as a senior design engineer at UltraDesign, LLC, Provo, Utah where he researched high-speed data converter circuits. He is currently with AMI Semiconductor in their RF CMOS group.     

A low-power, second-order Δ/Σ modulator using a single class-AB op-amp for voice-band applications

The design of a power-efficient second-order Δ/Σ modulator for voice-band is presented. At system level, a new single-loop, single-stage modulator is proposed. The modulator employs only one class-AB op-amp to realize a second-order noise shaping for voice-band applications. The modulator is designed in a 0.25μm standard CMOS process, and exhibits 86 dB dynamic range (DR) for a 4 kHz voice-bandwidth. The proposed modulator consumes 125μW from a 2.5 V supply. Aminghasem Safarian received the B.S. and M.S. degrees in electrical engineering from the Sharif University of Technology, in 2000, 2002, respectively. Since 2003 he is a research assistant at University of California, Irvine, working toward his Ph.D. degree in electrical engineering emphasizing on RF IC design for wireless communication systems. During the summer of 2005, he was with Broadcom Corporation, Irvine, CA, where he developed integrated receivers for RFID and WCDMA applications. Farzad Sahandiesfanjani was born in Tabriz, Iran in 1976. He received the B.S. and M.S. degrees in electronics from Sharif University of Technology, Tehran, Iran, in 1998 and 2000, respectively. The subject of his thesis was the design of 4th order cascade delta-sigma modulator for ADSL Analog Front End. From 1998 to 2003, he was with Emad Semicon Co., Tehran, Iran, where he designed circuits for voice application such as CODEC and SLIC chip. He also designed a 3rd order single loop class-D delta-sigma modulator for audio application. He joined Tripath Technology Inc., San Jose, CA, in 2003 and has been working on the design of analog and mixed-signal circuits for class-T audio power amplifier. He is also author of one patent for inductor-less switching audio power amplifier and also co-author of 3 more pending patents and 4 papers. Payam Heydari (S'98–M'00) received the B.S. and M.S. degrees (with honors) in electrical engineering from the Sharif University of Technology, in 1992, 1995, respectively. He received the Ph.D. degree in electrical engineering from the University of Southern California, in 2001. During the summer of 1997, he was with Bell-Labs, Lucent Technologies, Murray Hill, NJ, where he worked on noise analysis in deep submicron very large-scale integrated (VLSI) circuits. During the summer of 1998, he was with IBM T. J. Watson Research Center, Yorktown Heights, NY, where he worked on gradient-based optimization and sensitivity analysis of custom-integrated circuits. Since August 2001, he has been an Assistant Professor of Electrical Engineering at the University of California, Irvine, where his research interest is the design of high-speed analog, radio-frequency (RF), and mixed-signal integrated circuits. Dr. Heydari has received the 2005 National Science Foundation (NSF) CAREER Award, the 2005 IEEE Circuits and Systems Society Darlington Award, the 2005 Henry Samueli School of Engineering Teaching Excellence Award, the Best Paper Award at the 2000 IEEE International Conference on Computer Design (ICCD), the 2000 Honorable Award from the Department of EE-Systems at the University of Southern California, and the 2001 Technical Excellence Award in the area of Electrical Engineering from the Association of Professors and Scholars of Iranian Heritage (APSIH). He was recognized as the 2004 Outstanding Faculty at the EECS Department of the University of California, Irvine. His name was included in the 2006 Who's Who in America. Dr. Heydari is an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—part I. He currently serves on the Technical Program Committees of Custom Integrated Circuits Conference (CICC), International Symposium on Low-Power Electronics and Design (ISLPED), International Symposium on Quality Electronic Design (ISQED), and the Local Arrangement Chair of the ISLPED conference. He was the Student Design Contest Judge for the DAC/ISSCC Design Contest Award in 2003, the Technical Program Committee member of the IEEE Design and Test in Europe (DATE) from 2003 to 2004, and International Symposium on Physical Design (ISPD) in 2003. Mojtaba Atarodi received his Ph.D degree from USC (the University of Southern California, Los Angeles), in electrical engineering Electro-physics in 1993, his M.S from University of California at Irvine, and his B.SEE from the Tehran Polytechnic University with first Grade honor. Following his Ph.D completion, he was with Linear Technology Corporation from 1993 to 1996 as an analog design engineer. He has been with Sharif University of Technology as an Assistant and Visiting Professor since 1997. The Author of more than 50 technical journal and conference papers an a book on Analog CMOS IC Design, Dr Atarodi’s main research interests are analog and RF IC system, circuit, and signal processing design as well as analog synthesis tools. Having held several management and consulting positions during the last 15 years in the US industry, he holds one US patent in analog highly linear tunable Operational Transconductance Amplifiers and has applied for 5 more US patents as well.     

Network-Adaptive Video Communication Using Packet Path Diversity and Rate-Distortion Optimized Reference Picture Selection

In this paper, we present error-resilient Internet video transmission using path diversity and rate-distortion optimized reference picture selection. Under this scheme, the optimal packet dependency is determined adapting to network characteristics and video content, to achieve a better trade-off between coding efficiency and forming independent streams to increase error-resilience. The optimization is achieved within a rate-distortion framework, so that the expected end-to-end distortion is minimized under the given rate constraint. The expected distortion is calculated based on an accurate binary tree modeling with the effects of channel loss and error concealment taken into account. With the aid of active probing, packets are sent across multiple available paths according to a transmission policy which takes advantage of path diversity and seeks to minimize the loss rate. Experiments demonstrate that the proposed scheme provides significant diversity gain, as well as gains over video redundancy coding and the NACK mode of conventional reference picture selection. Yi Liang received the Ph.D. degree in Electrical Engineering from Stanford University in 2003. His expertise is in the areas of networked multimedia systems, real-time voice and video communication, and low-latency media streaming over the wire-line and wireless networks. Currently holding positions at Qualcomm CDMA Technologies, San Diego, CA, he is responsible for video and multimedia system design and development for Qualcomm's mobile station modem (MSM) chipsets. From 2000 to 2001, he conducted research with Netergy Networks, Inc., Santa Clara, CA, on voice over IP systems that provide improved quality over best-effort networks. From 2001 to 2003, he had been the lead of the Stanford - Hewlett-Packard Labs low-latency video streaming project, in which he and his colleagues developed error-resilience techniques for rich media communication over IP networks at low latency. In the summer of 2002 at Hewlett-Packard Labs, Palo Alto, CA, he developed an accurate loss-distortion model for compressed video and contributed in the development of the mobile streaming media content delivery network (MSM - CDN) that delivers rich media over 3G wireless. Yi Liang received the B. Eng. degree from Tsinghua University, Beijing, China. Eric Setton received the B.S. degree from Ecole Polytechnique, Palaiseau, France in 2001 and the M.S. degree, in Electrical Engineering from Stanford University in 2003. He is currently a Ph.D. candidate in the department of Electrical Engineering of Stanford University and is part of the Image, Video and Multimedia Systems group. Multimedia communication over wired and wireless networks, video compession and image processing are his main research interests. In 2001, he received the Carnot fellowship and the SAP Stanford Graduate fellowship. In 2003, he received the Sony SNRC fellowship. He has spent time in industry in France at SAGEM and in the United States at HP labs and at Sony Electronics. He has 4 patents pending. Bernd Girod is Professor of Electrical Engineering in the Information Systems Laboratory of Stanford University, California. He also holds a courtesy appointment with the StanfordDepartment of Computer Science and he serves as Director of the Image Systems Engineering Program at Stanford. His research interests include networked media systems, video signal compression and coding, and 3-d image analysis and synthesis. He received his M.S. degree in Electrical Engineering from Georgia Institute of Technology, in 1980 and his Doctoral degree “with highest honours” from University of Hannover, Germany, in 1987. Until 1987 he was a member of the research staff at the Institut fur Theoretische Nachrichtentechnik und Informationsverarbeitung, University of Hannover, working on moving image coding, human visual perception, and information theory. In 1988, he joined Massachusetts Institute of Technology, Cambridge, MA, USA, first as a Visiting Scientist with the Research Laboratory of Electronics, then as an Assistant Professor of Media Technology at the Media Laboratory. From 1990 to 1993, he was Professor of Computer Graphics and Technical Director of the Academy of Media Arts in Cologne, Germany, jointly appointed with the Computer Science Section of Cologne University. He was a Visiting Adjunct Professor with the Digital Signal Processing Group at Georgia Institute of Technology, Atlanta, GA, USA, in 1993. From 1993 until 1999, he was Chaired Professor of Electrical Engineering/Telecommunications at University of Erlangen-Nuremberg, Germany, and the Head of the Telecommunications Institute I, co-directing the Telecommunications Laboratory. He has served as the Chairman of the Electrical Engineering Department from 1995 to 1997, and as Director of the Center of Excellence “3-D Image Analysis and Synthesis” from 1995-1999. He has been a Visiting Professor with the Information Systems Laboratory of Stanford University, Stanford, CA, during the 1997/98 academic year. As an entrepreneur, Prof. Girod has worked successfully with several start-up ventures as founder, investor, director, or advisor. Most notably, he has been a co-founder and Chief Scientist of Vivo Software, Inc., Waltham, MA (1993–98); after Vivo's aquisition, 1998-2002, Chief Scientist of RealNetworks, Inc. (Nasdaq: RNWK); and, from 1996–2004, an outside Director of 8 × 8, Inc. (Nasdaq: EGHT). Prof. Girod has authored or co-authored one major text-book, two monographs, and over 250 book chapters, journal articles and conference papers in his field, and he holds about 20 international patents. He has served as on the Editorial Boards or as Associate Editor for several journals in his field, and is currently Area Editor for Speech, Image, Video and Signal Processing of the “IEEE Transactions on Communications.” He has served on numerous conference committees, e.g., as Tutorial Chair of ICASSP-97 in Munich and ICIP-2000 in Vancouver, as General Chair of the 1998 IEEE Image and Multidimensional Signal Processing Workshop in Alpbach, Austria, and as General Chair of the Visual Communication and Image Processing Conference (VCIP) in San Jose, CA, in 2001. Prof. Girod has been a member of the IEEE Image and Multidimensional Signal Processing Committee from 1989 to 1997 and was elected Fellow of the IEEE in 1998 ‘for his contributions to the theory and practice of video communications.’ He has been named ‘Distinguished Lecturer’ for the year 2002 by the IEEE Signal Processing Society. Together with J. Eggers, he is recipient of the 2002 EURASIP Best Paper Award.     

New layout strategies with improved matching performance

In this paper, the systematic mismatch error in integrated circuits due to gradient effects is modeled and analyzed. Three layout strategies with improved matching performance are reviewed and summarized. The hexagonal tessellation pattern can cancel quadratic gradient errors with only 3 units for each device and has high area-efficiency when extended. Both the Nth-order circular symmetry patterns and Nth-order central symmetry patterns can cancel up to Nth-order gradient effects between two devices using 2^N unit cells for each one. Among these three techniques, the central symmetry patterns have the best-reported matching performance for Manhattan structures; the circular-symmetry patterns have the best theoretical matching performance; and the hexagonal tessellation pattern has high density and high structural stability. The Nth-order central symmetry technique is compatible to all IC fabrication processes requiring no special design rules. Simulation results of these proposed techniques show better matching characteristics than other existing layout techniques under nonlinear gradient effects. Specifically, two pairs of P-poly resistors using 2nd and 3rd-order central symmetry patterns were fabricated and tested. Less than 0.04% mismatch and less than 0.002% mismatch were achieved for the 2nd and the 3rd-order structures, respectively. Chengming He was born in YiWu, China in 1976. He received his B.S. in 1999 in Electronic Engineering department and his M.S. degree in the institute of Microelectronics in 2001 at Tsinghua University, Beijing. He started to work toward his PhD in Iowa State University since August 2001. Since June 2004 he started to work as a design engineer in Silicon Laboratories, Inc., Austin, TX. He studied and designed LNA, band-pass filter and on-chip power management blocks as well as matching-enhanced layout patterns. He is interested in designing high gain low voltage amplifier, high speed power-efficient ADC and high speed high linear DAC as well as other mixed-signal circuits. He is also interested in the application of nonlinear system dynamical theory in mixed-signal design and yield-enhancement by improving layout matching. He has published more than 10 technical papers. He was a student member of IEEE from 01--04 and now is a member. He is a member of Tau Beta Pi. Xin Dai was born in Shanghai, China on March 11, 1981. She received the B.Eng. in 2003 from Shanghai Jiao Tong University, Shanghai, China. She is currently a graduate student in Department of Electrical and Computer Engineering at Iowa State University, Ames, IA. Her research has been connected to data converter design and calibrations, layout techniques and build-in-self-test. Xin Dai is now taking a summer-intern in Broadcom Corp., CA. Hanqing Xing was born in Dalian, China, in 1978. He received the B.S. and M.S. degrees with honors in Electronic Engineering from Tsinghua University, Beijing, China, in 2000 and 2003, respectively. He is currently a PhD student at Iowa State University working in analog and mixed signal design group. His research interests include analog, mixed-signal, and data-conversion integrated circuits design and test. Degang Chen received his B.S. degree in 1984 in Instrumentation and Automation from Tsinghua University, Beijing, China and his M.S. and Ph.D. degrees in 1988 and 1992, respectively, both in Electrical and Computer Engineering, from the University of California, Santa Barbara. From 1984 to 1986, he was with the Beijing Institute of Control Engineering, a space industry R/D institute. From March 1992 to August 1992, he was the John R. Pierce Instructor of Electrical Engineering at California Institute of Technology. After that, he joined Iowa State University where he is currently an Associate Professor. He was with the Boeing Company in summer of 1999 and was with Dallas Semiconductor-Maxim in summer of 2001. His research experience include particulate contamination in microelectronic processing systems, vacuum robotics in microelectronics, adaptive and nonlinear control of electromechanical systems, and dynamics and control of atomic force microscopes. His current teaching and research interests are in the area of analog and mixed-signal VLSI integrated circuit design and testing. In particular, he is interested in low-cost high-accuracy testing and built-in-self-test of analog and mixed-signal and RF circuits, and in self-calibration and adaptive reconfiguration/repair strategies for performance and yield enhancement. Dr. Chen is the recipient of the Best Paper Award at the 1990 IEEE Conference on Decision and Control and the Best Transaction Paper Award from the ASME Journal of Dynamic Systems, Measurement, and Control in 1995. He was selected an A.D. Welliver Faculty Fellow with the Boeing Company in 1999.     

2005

In recent years, wireless Internet service providers (WISPs) have established Wi-Fi hotspots in increasing numbers at public venues, providing local coverage to traveling users and empowering them with the ability to access email, Web, and other Internet applications on the move. In this paper, we observe that while the mobile computing landscape has changed both in terms of number and type of hotspot venues, there are several technological and deployment challenges remaining before hotspots can become an ubiquitous infrastructure. These challenges include authentication, security, coverage, management, location services, billing, and interoperability. We discuss existing research, the work of standards bodies, and the experience of commercial hotspot providers in these areas, and then describe compelling open research questions that remain. Anand Balachandran has been a member of the research staff at Intel Research, Seattle since October 2003. His research interests include wireless networking systems, wireless Internet, infrastructure and ad-hoc networks, and mobile and ubiquitous computing. He received his Bachelor of Technology degree from the Indian Institute of Technology, Madras in 1995, his Master’s degree from Columbia University, in 1997, and his Ph.D. degree in Computer Science and Engineering from the University of California at San Diego in 2003. Geoffrey M. Voelker is an assistant professor at the University of California at San Diego. His research interests include operating systems, distributed systems, networking, and mobile computing. He received a BS degree in Electrical Engineering and Computer Science from the University of California at Berkeley in 1992, and the M.S. and Ph.D. degrees in Computer Science and Engineering from the University of Washington in 1995 and 2000, respectively. In 2000, he received the first Computing Research Association (CRA) Digital Government Fellowship, and in 2002 he received the Hellman Young Faculty Fellowship at UCSD. Victor Bahl is a Senior Researcher and the Manager of the Networking Group in Microsoft Research. His research interests span a variety of problems in wireless networking. In addition to making many product contributions, he has authored over 65 scientific papers, 44 issued and pending patent applications and several book chapters. He is the co-founder and Chairman of the ACM Special Interest Group in Mobility (SIGMOBILE); the founder and past Editor-in-Chief of ACM Mobile Computing and Communications Review, and the founder and Steering Committee Chair of ACM/USENIX Mobile Systems Conference (MobiSys); He has served on the editorial board of IEEE Journal on Selected Areas in Communications, and is currently serving on the editorial boards of Elsevier’s Adhoc Networking Journal, Kulwer’s Telecommunications Systems Journal, and ACM’s Wireless Networking Journal. He has served as a guest editor for several IEEE and ACM journals and on networking review panels organized by the National Science Foundation (NSF), the National Research Council (NRC) and European Union’s COST. He has served as the General Chairman, Program Chair and Steering Committee member of several IEEE and ACM conferences and on the Technical Program Committee of over 45 international conferences and workshops. He is the recipient of Digital’s Doctoral Engineering Award (1994) and ACM SIGMOBILE’s Distinguished Service Award (2001). He is a Fellow of the ACM, a Senior Member of the IEEE and a past president of the electrical engineering honor society Eta kappa Nu-Zeta Pi. Dr. Bahl received his Ph. D in Computer Systems Engineering from the University of Massachusetts Amherst.This revised version was published online in August 2005 with a corrected cover date.     

Low-Cost Testing of 5 GHz Low Noise Amplifiers Using New RF BIST Circuit

This paper presents a new low-cost RF BIST (Built-In Self-Test) scheme that is capable of measuring input impedance, gain, noise figure and input return loss for a low noise amplifier (LNA) in RF systems. The RF BIST technique requires an additional RF amplifier and two peak detectors, and its output is a DC voltage level. The BIST circuit is designed using 0.18 μm SiGe technology. The test technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the developed mathematical equations. Simulation results are presented for an LNA working at 5 GHz. Measurement data are compared with simulation results to validate the developed mathematical equations. The technique is simple and inexpensive. Jee-Youl Ryu received the BS and MS degrees in 1993 and 1997 from Pukyong National University in Electronic Engineering, Pusan, South Korea respectively. He also received the PhD degree in 2004 from Arizona State University in Electrical Engineering, Arizona, USA. He is currently with Samsung SDI Co., Ltd. His current research interests include RF IC design and testing, MMIC design and testing, analog IC design and testing, passives modeling, testing and analysis, and MEMS technology. Dr. Bruce Kim received the B.S.E.E. degree from the University of California, Irvine in 1981, the M.S. degree in electrical engineering from the University of Arizona in 1985, and the Ph.D. degree in electrical engineering from Georgia Institute of Technology in 1996. He was an Associate Professor at Arizona State University until 2005. Currently, he is an Associate Professor at The University of Alabama. His current research interests include RF IC testing, MEMS integration and VLSI circuits. He has been working on SiP testing technologies, package electrical modeling, and measurements of RF IC packages. Dr. Kim is a 1997 recipient of the National Science Foundation's CAREER Award and received the Meritorious Award from IEEE. He serves as the Chair of the IEEE CPMT Society TC-Electrical Test, associate editor of the IEEE Transactions on Advanced Packaging, associate editor of Design and Test of Computers, and program committee member of Electronic Components and Technology Conference. He is a senior member of IEEE.     

SOLONet: Sub-optimal location-aided overlay network for MANETs

Overlay networks have made it easy to implement multicast functionality in MANETs. Their flexibility to adapt to different environments has helped in their steady growth. Overlay multicast trees that are built using location information account for node mobility and have a low latency. However, the performance gains of such trees are offset by the overhead involved in distributing and maintaining precise location information. As the degree of (location) accuracy increases, the performance improves but the overhead required to store and broadcast this information also increases. In this paper, we present SOLONet, a design to build a sub-optimal location aided overlay multicast tree, where location updates of each member node are event based. Unlike several other approaches, SOLONet doesn’t require every packet to carry location information or each node maintain location information of every other node or carrying out expensive location broadcast for each node. Our simulation results indicate that SOLONet is scalable and its sub-optimal tree performs very similar to an overlay tree built by using precise location information. SOLONet strikes a good balance between the advantages of using location information (for building efficient overlay multicast trees) versus the cost of maintaining and distributing location information of every member nodes. Abhishek Patil received his BE degree in Electronics and Telecommunications Engineering from University of Mumbai (India) in 1999 and an MS in Electrical and Computer Engineering from Michigan State University in 2002. He finished his PhD in 2005 from the Department of Computer Science and Engineering at Michigan State University. He is a research engineer at Kiyon, Inc. located in San Diego, California. His research interests include wireless mesh networks, UWB, mobile ad hoc networks, application layer multicast, location-aware computing, RFIDs, and pervasive computing. Yunhao Liu received his BS degree in Automation Department from Tsinghua University, China, in 1995, and an MA degree in Beijing Foreign Studies University, China, in 1997, and an MS and a Ph.D. degree in Computer Science and Engineering at Michigan State University in 2003 and 2004, respectively. He is now an assistant professor in the Department of Computer Science at Hong Kong University of Science and Technology. His research interests include wireless sensor networks, peer-to-peer and grid computing, pervasive computing, and network security. He is a senior member of the IEEE Computer Society. Li Xiao received the BS and MS degrees in computer science from Northwestern Polytechnic University, China, and the PhD degree in computer science from the College of William and Mary in 2002. She is an assistant professor of computer science and engineering at Michigan State University. Her research interests are in the areas of distributed and Internet systems, overlay systems and applications, and sensor networks. She is a member of the ACM, the IEEE, the IEEE Computer Society, and IEEE Women in Engineering. Abdol-Hossein Esfahanian received his B.S. degree in Electrical Engineering and the M.S. degree in Computer, Information, and Control Engineering from the University of Michigan in 1975 and 1977 respectively, and the Ph.D. degree in Computer Science from Northwestern University in 1983. He was an Assistant Professor of Computer Science at Michigan State University from September 1983 to May 1990. Since June 1990, he has been an Associate Professor with the same department, and from August 1994 to May 2004, he was the Graduate Program Director. He was awarded ‘The 1998 Withrow Exceptional Service Award’, and ‘The 2005 Withrow Teaching Excellence Award’. Dr. Esfahanian has published articles in journals such as IEEE Transactions, NETWORKS, Discrete Applied Mathematic, Graph Theory, and Parallel and Distributed Computing. He was an Associate Editor of NETWORKS, from 1996 to 1999. He has been conducting research in applied graph theory, computer communications, and fault-tolerant computing. Lionel M. Ni earned his Ph.D. degree in electrical and computer engineering from Purdue University in 1980. He is Chair Professor and Head of Computer Science and Engineering Department of the Hong Kong University of Science and Technology. His research interests include wireless sensor networks, parallel architectures, distributed systems, high-speed networks, and pervasive computing. A fellow of IEEE, Dr. Ni has chaired many professional conferences and has received a number of awards for authoring outstanding papers.     

A Network Layer Approach to Enable TCP over Multiple Interfaces

The mobile Internet is set to become ubiquitous with the deployment of various wireless technologies. When heterogeneous wireless networks overlap in coverage, a mobile terminal can potentially use multiple wireless interfaces simultaneously. In this paper, we motivate the advantages of simultaneous use of multiple interfaces and present a network layer architecture that supports diverse multi-access services. Our main focus is on one such service provided by the architecture: Bandwidth Aggregation (BAG), specifically for TCP applications.While aggregating bandwidth across multiple interfaces can improve raw throughput, it introduces challenges in the form of packet reordering for TCP applications. When packets are reordered, TCP misinterprets the duplicate ACKS received as indicative of packet loss and invokes congestion control. This can significantly lower TCP throughput and counter any gains that can be had through bandwidth aggregation. To improve overall performance of TCP, we take a two-pronged approach: (1) We propose a scheduling algorithm that partitions traffic onto the different paths (corresponding to each interface) such that reordering is minimized. The algorithm estimates available bandwidth and thereby minimizes reordering by sending packet pairs on the path that introduces the least amount of delay. (2) A buffer management policy is introduced at the client to hide any residual reordering from TCP. We show through simulations that our network-layer approach can achieve good bandwidth aggregation under a variety of network conditions.Kameswari Chebrolu is an assistant professor in the electrical department of Indian Institute of Technology, Kanpur. Her research interests are in the areas of wireless network architecture, protocol design and analysis. Kameswari obtained her M.S. and Ph.D. degree in Electrical and Computer Engineering from University of California at San Diego, in 2001 and 2004 respectively.Bhaskaran Raman received his B.Tech in Computer Science and Engineering from Indian Institute of Technology, Madras in May 1997. He received his M.S. and Ph.D. in Computer Science from University of California, Berkeley, in 1999 and 2002 respectively. He joined as faculty in the CSE department at Indian Institute of Technology, Kanpur (India) starting June 2003. His research interests and expertise are in communication networks, wireless/mobile networks, large-scale Internet-based systems, and Internet middleware services.Ramesh R. Rao is a professor at the University of California, San Diego (UCSD). He is a member of the faculty of Irwin and Joan Jacobs School of Engineering, since 1984. Professor Rao is the former director of UCSD’s Center for Wireless Communications (CWC), and the current Director of the San Diego Division of the California Institute of Telecommunications and Information Technology [Cal-(IT)²]. As Director of the San Diego Division of Cal-(IT)², he leads several interdisciplinary, collaborative projects. His research interests include architectures, protocols and performance analysis of computer and communication networks, and he has published extensively on these topics. He received his B.E. from the University of Madras and his M.S. and Ph.D. from the University of Maryland at College Park. Most recently, Dr. Rao was honored by being appointed the first holder of the Qualcomm Endowed Chair in Telecommunications and Information Technologies.     

Statistically assisted routing algorithms (SARA) for hop count based forwarding in wireless sensor networks

The main goal of this paper is to provide routing–table-free online algorithms for wireless sensor networks (WSNs) to select cost (e.g., node residual energies) and delay efficient paths. As basic information to drive the routing process, both node costs and hop count distances are considered. Particular emphasis is given to greedy routing schemes, due to their suitability for resource constrained and highly dynamic networks. For what concerns greedy forwarding, we present the Statistically Assisted Routing Algorithm (SARA), where forwarding decisions are driven by statistical information on the costs of the nodes within coverage and in the second order neighborhood. By analysis, we prove that an optimal online policy exists, we derive its form and we exploit it as the core of SARA. Besides greedy techniques, sub–optimal algorithms where node costs can be partially propagated through the network are also presented. These techniques are based on real time learning LRTA algorithms which, through an initial exploratory phase, converge to quasi globally optimal paths. All the proposed schemes are then compared by simulation against globally optimal solutions, discussing the involved trade–offs and possible performance gains. The results show that the exploitation of second order cost information in SARA substantially increases the goodness of the selected paths with respect to fully localized greedy routing. Finally, the path quality can be further increased by LRTA schemes, whose convergence can be considerably enhanced by properly setting real time search parameters. However, these solutions fail in highly dynamic scenarios as they are unable to adapt the search process to time varying costs. Michele Rossi was born in Ferrara, Italy on October 30th, 1974. He received the Laurea degree in Electrical Engineering (with honors) and the Ph.D. degree in Information Engineering from the University of Ferrara in 2000 and 2004, respectively. Since 2000 he has been a Research Fellow at the Department of Engineering of the University of Ferrara. During 2003 he was on leave at the Center for Wireless Communications (CWC) at the University of California San Diego (UCSD), where he did research on wireless sensor networks. In November 2005 he joined the Department of Information Engineering of the University of Padova, Italy, where he is currently an Assistant Professor. Michele Rossi is currently part of the EU funded Ambient Networks and eSENSE projects. His research interests include: TCP/IP protocols over wireless networks, performance analysis of link layer retransmission techniques, routing and access selection in heterogeneous wireless networks and MAC/routing algorithms for wireless sensor networks. Michele Zorzi was born in Venice, Italy, in 1966. He received the Laurea degree and the Ph.D. degree in Electrical Engineering from the University of Padova, Italy, in 1990 and 1994, respectively. During the Academic Year 1992/93, he was on leave at the University of California, San Diego (UCSD), attending graduate courses and doing research on multiple access in mobile radio networks. In 1993, he joined the faculty of the Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy. After spending three years with the Center for Wireless Communications at UCSD, in 1998 he joined the School of Engineering of the University of Ferrara, Italy, and in 2003 joined the Department of Information Engineering of the University of Padova, Italy, where he is currently a Professor. His present research interests include performance evaluation in mobile communications systems, random access in mobile radio networks, ad hoc and sensor networks, and energy constrained communications protocols. Dr. Zorzi from 2003 to 2005 was the Editor-In-Chief of the IEEE Wireless Communications Magazine, and currently serves on the Editorial Boards of the IEEE Transactions on Communications, the IEEE Transactions on Wireless Communications, the IEEE Transactions on Mobile Computing, the Wiley Journal of Wireless Communications and Mobile Computing and the ACM/URSI/Kluwer Journal of Wireless Networks. He was also guest editor for special issues in the IEEE Personal Communications Magazine (Energy Management in Personal Communications Systems) and the IEEE Journal on Selected Areas in Communications (Multi-media Network Radios). Ramesh R. Rao was born in Sindri, India, where he completed his undergraduate work at the Regional Engineering College of the University of Madras in Tiruchirapalli, obtaining a BE (Honors) degree in Electronics and Communications in 1980. He completed his graduate work at the University of Maryland, College Park, Maryland where he received his M.S. and Ph.D. Professor Rao is currently a Professor at the University of California, San Diego (UCSD) at the department of Electrical and Computer Engineering in the Irwin and Joan Jacobs School of Engineering, where he has been a member of the faculty since 1984. Professor Rao is the former director of UCSD’s Center for Wireless Communications (CWC), and currently serves as the Qualcomm Endowed Chair in Telecommunications and Information Technologies, and as the Director of the San Diego Division of the California Institute of Telecommunications and Information Technology [Cal-(IT)²]. As Director of the San Diego Division of Cal-(IT)², he leads several interdisciplinary and collaborative projects. His research interests include architectures, protocols and performance analysis of computer and communication networks, and he has published extensively on these topics. Since 1984, Professor Rao has authored over 100 technical papers, contributed book chapters, conducted a number of short courses and delivered invited talks and plenary lectures. He is currently supervising both masters and doctoral students.     

Analysis of Dataflow Programs with Interval-limited Data-rates

In this paper, we consider the problem of analyzing dataflow programs with the property that actor production and consumption rates are not constant and fixed, but limited by intervals. Such interval ranges may result from uncertainty in the specification of an actor or as a design freedom of the model. Major questions such as consistencyand buffer memory requirementsfor single-processor scheduleswill be analyzed here for such specifications for the first time. Also, metamodeling formulations of interval limited dataflow are discussed, with special emphasis on the application to cyclo-static dataflow modeling. Jürgen Teich received his masters degree (Dipl.-Ing.) in 1989 from the University of Kaiserslautern (with honours). From 1989 to 1993, he was PhD student at the University of Saarland, Saarbrücken, Germany from where he received his PhD degree (summa cum laude). His PhD thesis entitled ‘A Compiler for Application-Specific Processor Arrays‘summarizes his work on techniques for mapping computation intensive algorithms onto dedicated VLSI processor arrays. In 1994, Dr. Teich joined the DSP design group of Prof. E. A. Lee and D.G. Messerschmitt in the Department of Electrical Engineering and Computer Sciences (EECS) at UC Berkeley where he was working in the Ptolemy project (PostDoc). From 1995 to 1998, he held a position at Institute of Computer Engineering and Communications Networks Laboratory (TIK) at ETH Zürich, Switzerland, finishing his Habilitation entitled ‘Synthesis and Optimization of Digital Hardware Software Systems’ in 1996. From 1998 to 2002, he was full professor in the Electrical Engineering and Information Technology department of the University of Paderborn, holding a chair in Computer Engineering. Since 2003, he is appointed full professor in the Computer Science Institute of the Friedrich-Alexander University Erlangen-Nuremberg holding a chair in Hardware-Software-Co-Design. Dr. Teich has been a member of multiple program committees of well-known conferences and workshops. He is member of the IEEE and author of a textbook on Co-Design edited by Springer in 1997.His research interests are massive parallelism, embedded systems, Co-Design, and computer architecture. Since 2004, Prof. Teich is also an elected reviewer for the German Science Foundation (DFG) for the area of Computer Architecture and Embedded Systems. Prof. Teich is involved in many interdisciplinary national basic research projects as well as industrial projects. He is supervising 19 PhD students currently. Shuvra S. Bhattacharyyais an associate professor in the Department of Electrical and Computer Engineering and the Institute for Advanced Computer Studies (UMIACS) at the University of Maryland, College Park. He is also an affiliate associate professor in the Department of Computer Science. Dr. Bhattacharyya is coauthor or coeditor of four books and the author or coauthor of more than 100 refereed technical articles. His research interests include VLSI signal processing, embedded software, and hardware/software co-design. He received the B.S. degree from the University of Wisconsin at Madison, and the Ph.D. degree from the University of California at Berkeley. Dr. Bhattacharyya has held industrial positions as a Researcher at the Hitachi America Semiconductor Research Laboratory (San Jose, California), and as a Compiler Developer at Kuck & Associates (Champaign, Illinois).     

Design of an ADC for subsampling video applications

This paper describes a 10 bit 30 Msample/s (MSPS) CMOS analog-to-digital converter (ADC) for high-speed signal processing, especially for subsampling applications, for example digital video broadcasting over cable (DVB-C), terrestrial (DVB-T) and handheld (DVB-H) systems. The proposed pipelined ADC shows a good figure-of-merit (FoM). It adopts a power efficient amplifier sharing technique, a symmetrical gate-bootstrapping technique with modified timing for the bottom-sampling switch of a wideband sample-and-hold (S/H) circuit, a proposed stable high-swing bias circuit for a wide-swing gain-boosting telescopic amplifier. The measured differential and integral nonlinearities of the prototype in a 0.25-μm CMOS technology show less than 0.4 least significant bit (LSB) and 0.85 LSB respectively at full sampling rate. The ADC exhibits higher than 9 effective number of bits (ENOB) for input frequencies up to about 60 MHz, which is the fourfold Nyquist rate (fs/2), at 30 MSPS. The ADC consumes 60 mW from a 3-V supply and occupies about 1.36 mm². Jian Li received the Bachelor of Engineering (B.E.) degree in electronic engineering from Xi’an Jiaotong University, Xi’an, China, in 2003. He is currently working toward the Ph.D. degree at Microelectronics department, Fudan University, Shanghai, China. His current research interest is high-speed high resolution A/D converter design. Xiaoyang Zeng was born in Hunan Province, P.R. China on April 17, 1972. He received the B.S. degree from Xiangtan University, China in 1992, and the Ph.D. degree from Changchun Institute of Optics and Fine Mechanics, Chinese Academy of Sciences in 2001. From 2001 to 2003, he worked as a post-doctor researcher at the State-Key Lab of ASIC & System, Fudan University, P.R. China. Then he joined the faculty of Department of Micro-electronics at Fudan University as an associate professor. His research interests include information security chip design, VLSI signal processing, and communication systems. Prof. Zeng is the Chair of Design-Contest of ASP-DAC 2004 and 2005, also the TPC member of several international conferences such as ASCON 2005 and A-SSCC 2006, etc. Jianyun Zhang received the B.S., M.S. and Ph.D degree in electrical engineering from Fudan University, Shanghai, China in 1997, 2000 and 2006 respectively. From 2000 to 2002, he was with Alcatel microelectronics, Belgium, where he was involved in circuit design for GSM and GPRS. In 2002, he joined Trident microsystem, where he concentrated on the design of Video AFE including data converters and mixed signal circuits. In 2005, he joined Shihong microelectronics Corp., where he is now a director of mixed signal IC for video high speed interface. His research interests include data conversion, HDMI SerDes, and analog circuit design. Lei Xie received the Bachelor of Science (B.S.) degree in microelectronics from Nankai University, Tianjin, China, in 2005. He is currently working toward the M.S. degree at Fudan University, Shanghai, China. His current research interest is high-speed high resolution A/D converter. Huan Deng received the B.S. degree in microelectronics from Fudan University, Shanghai, P.R. China, in 2003. He is currently working toward the M.S. degree in microelectronics at the State Key Lab of ASIC & System, Fudan University. He is currently involved in the design of low-power, high-speed PLL’s. Yawei Guo received the B.S. and M.S. degree in electrical engineering from Fudan University in 1999 and 2002 respectively. From 2002 to August 2003, he was with Philips Semiconductors in Shanghai. Since August 2003, he has been with Shanghai MicroScience Integrated Circuits Co., Ltd., based in Shanghai, P. R. China. He has been leading a group and developing analog and mixed signal circuits. His research interests include high-speed data communication, data converters, and phase locked loops.     

Performance of Multilayered Video Encoding and Delivery over Lossy Channels Using a Joint Source-Channel Coding Approach

In this paper, the performance of selected error-control schemes based on forward error-control (FEC) coding for H.263+ video transmission over an additive white Gaussian noise (AWGN) channel is studied. Joint source and channel coding (JSCC) techniques that employ single-layer and 2-layer H.263+ coding in conjunction with unequal error protection (UEP) to combat channel errors are quantitatively compared. Results indicate that with appropriate joint source and channel coding, tailored to the respective layers, FEC-based error control in combination with 2-layer video coding techniques can lead to more acceptable quality for wireless video delivery in the presence of channel impairments. Yong Pei is currently a tenure-track assistant professor in the Computer Science and Engineering Department, Wright State University, Dayton, OH. Previously he was a visiting assistant professor in the Electrical and Computer Engineering Department, University of Miami, Coral Gables, FL. He received his B.S. degree in electrical power engineering from Tsinghua University, Beijing, in 1996, and M.S. and Ph.D. degrees in electrical engineering from Rensselaer Polytechnic Institute, Troy, NY, in 1999 and 2002, respectively. His research interests include information theory, wireless communication systems and networks, and image/video compression and communications. He is a member of IEEE and ACM. James W. Modestino (S′67- M′73- SM′81- F′87) was born in Boston, MA, on April 27, 1940. He received the B.S. degree from Northeastern University, Boston, MA, in 1962, and the M.S. degree from the University of Pennsylvania, Philadelphia, PA, in 1964, both in electrical engineering. He also received the M.A. and Ph.D. degrees from Princeton University, Princeton, NJ, in 1968 and 1969, respectively. He has held a number of industrial positions, including positions with RCA Communications Systems Division, Camden, NJ; General Electronic Laboratories, Cambridge, MA; AVCO Systems Division, Wilmington, MA; GTE Laboratories, Waltham, MA; and MIT Lincoln Laboratories, Lexington, MA. From 1970 to 1972, he was an Assistant Professor in the Department of Electrical Engineering, Northeastern University. In 1972, he joined Rensselaer Polytechnic Institute, Troy, NY, where until leaving in 2002 he was an Institute Professor in the Electrical, Computer and Systems Engineering Department and Director of the Center for Image Processing Research. He has been responsible for teaching and research in the communication, information and signal processing systems area. His specific research interests include communication in fading dispersive channels; detection, estimation and filtering in impulsive or burst noise environments; digital signal, image and video processing; and multimedia communication systems and networks. In 2002 he joined the Department of Electrical and Computer Engineering at the University of Miami, Coral Gables, FL, as the Victor E. Clarke Endowed Scholar, Professor and Chair. He has held visiting positions with the University of California at San Diego, LaJolla, CA (1981–1982); GE Research and Development Center, Schenectady, NY (1988–1989); and Massachusetts Institute of Technology, Cambridge, MA (1995–1996). Dr. Modestino is a past member of the Board of Governors of the IEEE Information Theory Group. He is a past Associate Editor and Book Review Editor for the IEEE TRANSACTIONS ON INFORMATION THEORY. In 1984, he was co-recipient of the Stephen O. Rice Prize Paper Award from the IEEE Communications Society and in 2000 he was co-recipient of the best paper award at the International Packet Video Conference.     

Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI

This paper presents a detailed scaling analysis of the power supply distribution network voltage drop in DSM technologies. The effects of chip temperature, electromigration and interconnect technology scaling (including resistivity increase of Cu interconnects due to electron surface scattering and finite barrier thickness) are taken into consideration during this analysis. It is shown that the voltage drop effect in the power/ground (P/G) distribution network increases rapidly with technology scaling, and that using well-known countermeasures such as wire-sizing and/or decoupling capacitor insertion which are typically used in the present design methodologies may be insufficient to limit the voltage fluctuations over the power grid for future technologies. It is also shown that such voltage drops on power supply lines of switching devices in a clock distribution network can introduce significant amount of skew which in turn degrades the signal integrity.This work was done when the author was with the Dept. of EESystems, University of Southern California.Amir H. Ajami received his B.S. degree in electrical engineering from the University of Tehran, Tehran, Iran in 1993. He received his M.S. and Ph.D. degrees in electrical engineering from the University of Southern California, Los Angeles, CA, in 1999 and 2002, respectively.He is currently a member of consulting staff in research and development division at MagmaDesign Automation, Inc., Santa Clara, CA. He has previously held positions at Cadence Design Systems, Inc., andMagma Design Automations, Inc., in 1999 and 2000, respectively. His research interests are in the area of technology scaling issues in high-performance VLSI designs with emphasis on full-chip thermal analysis, thermalaware timing and power optimization methodologies, and signal integrity. He has coauthored several papers on the modeling and analysis of the effects of substrate thermal gradients on performance degradation and development of thermal-aware physical-synthesis optimization algorithms.Dr. Ajami is a member of Association of Computing Machinery (ACM) and IEEE. HE serves on the technical program committee of the 2005 IEEE International Symposium on Quality Electronics Design.Kaustav Banerjee received the Ph.D. degree in electrical engineering and computer sciences from the University of California at Berkeley in 1999. He was with Stanford University, Stanford, CA, from 1999 to 2002 as a Research Associate at the Center for Integrated Systems. In July 2002, he joined the faculty of the Electrical and Computer Engineering Department at the University of California, Santa Barbara, as an Assistant Professor. From February 2002 to August 2002 he was a Visiting Professor at the Circuit Research Labs of Intel in Hillsboro, Oregon. In the past, he has also held summer/visiting positions at Texas Instruments Inc., Dallas, Texas, Fujitsu Labs and the Swiss Federal Institute of Technology (EPFL). His present research interests focus on a wide variety of nanometer scale issues in high-performance VLSI and mixed-signal designs, as well as on circuits and systems issues in emerging nanoelectronics. He is also interested in some exploratory interconnect and circuit architectures including 3-D ICs. At UCSB, Dr. Banerjee mentors several doctoral and masters students. He also co-advises graduate students at Stanford University, University of Illinois at Urbana-Champaign and EPFL-Switzerland. He has co-directed two doctoral dissertations at Stanford University and the University of Southern California. Dr. Banerjee served as Technical Program Chair of the 2002 IEEE International Symposium on Quality Electronic Design (ISQED 02), and is the General Chair of ISQED 05. He also serves or has served on the technical program committees of the IEEE International Electron Devices Meeting, the IEEE International Reliability Physics Symposium, the EOS/ESD Symposium and the ACM International Symposium on Physical Design. His research has been chronicled in over 100 journals and refereed international conference papers and a book chapter. He has also co-edited a book titled Emerging Nanoelectronics: Life with and after CMOS by Kluwer in 2004. Dr. Banerjee has been recognized through the ACM SIGDA Outstanding New Faculty Award (2004) as well as a Best Paper Award at the Design Automation Conference (2001). He is listed in Whos Who in America and Whos Who in Science and Engineering.Massoud Pedram received a B.S. degree in Electrical Engineering from the California Institute of Technology in 1986 and M.S. and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley in 1989 and 1991, respectively. He then joined the department of Electrical Engineering, Systems at the University of Southern California where he is currently a professor. Dr. Pedram has served on the technical program committee of a number of conferences, including the Design automation Conference (DAC), Design and Test in Europe Conference (DATE), Asia-Pacific Design automation Conference (ASP-DAC), and International Conference on Computer Aided Design (ICCAD). He served as the Technical Co-chair and General Co-chair of the International Symposium on Low Power Electronics and Design (SLPED) in 1996 and 1997, respectively. He was the Technical Program Chair and the General Chair of the 2002 and 2003 International Symposium on Physical Design. Dr. Pedram has published four books, 60 journal papers, and more than 150 conference papers. His research has received a number of awards including two ICCD Best Paper Awards, a Distinguished Citation from ICCAD, a DAC Best Paper Award, and an IEEE Transactions on VLSI Systems Best Paper Award. He is a recipient of the NSFs Young Investigator Award (1994) and the Presidential Faculty Fellows Award (a.k.a. PECASE Award) (1996).Dr. Pedram is a Fellow of the IEEE, a member of the Board of Governors for the IEEE Circuits and systems Society, an associate editor of the IEEE Transactions on Computer Aided Design, the IEEE Transactions on Circuits and Systems, and the IEEE Circuits and Systems Society Distinguished Lecturer Program Chair. He is also an Advisory Board Member of the ACM Interest Group on Design Automation, and an associate editor of the ACM Transactions on Design Automation of Electronic Systems. His current work focuses on developing computer aided design methodologies and techniques for low power design, synthesis, and physical design. For more information, please go to URL address: .     

A Novel CMOS Realization of the Differential Input Balanced Output Current Operational Amplifier and its Applications

In this paper a new realization of the differential input balanced output current opamp is proposed, operating with ±1.5 V supplies. Its architecture is based on the use of current inverters to sense the input currents while providing a very low input resistance, 23 Ω. The opamp provides a maximum output swing of 700 μA, with an input offset current of 3.5 nA. The differential gain achieved is 65.5 dB, and the differential structure adopted in the design provided a high CMRR, 89.5 dB, the proposed circuit is compared to other realizations with single and differential inputs. The applications of the current opamp are exploited some new applications are presented such as: MOSFET-C integrators, full non-linearity cancellation for MOS transistors, and finally a digitally tuned current-mode variable gain amplifier, which has a gain tuning range of 25 dB with a 0.05 dB step.Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964, the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA, U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering.He is currently Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985–1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987–1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo.He was a visiting scholar at Bochum University, Germany (Summer, 1985) and with the Technical University of Wien, Austria (Summer, 1987).In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr. Soliman is a member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Presently Dr. Soliman is Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters).     

A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices

This paper extends the timing test model in [5] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, Parallel/Serial RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a test escape of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter. Baosheng Wang received his B.S. degree from Beijing University of Aeronautics and Astronautics (BUAA), Beijing, P.R. China, in 1997 and M.S. degree from Precision Instrument & Mechanical Engineering from the Tsinghua University, Beijing, P. R. China in 2000. In 2005, he received his Ph.D. degree in Electrical Engineering from the University of British Columbia (UBC), Vancouver, BC, Canada. During his Master study, he was doing MEMS, Micro Sensors and Digital Signal processing. From 2000 to 2001, he worked in Beijing Gaohong Telecommunications Company as a hardware engineer in ATM technology. Currently, he is a Design-for-Test (DFT) engineer at ATI Technologies Inc., Markham, Ontario, Canada. He publishes widely at international conferences and journals. His primary research interests are time-driven or timing-oriented testing methodologies for System on-a-Chip (SoC). These fields include test time reduction for SRAMs, accelerated reliability test for non-volatile memories, yield analysis for SoC timing tests, SoC path delay timing characterization and embedded timing measurements. Andy Kuo is currently a Ph.D student of System on a Chip (SoC) Research Lab at the Department of Electrical and Computer Engineering, University of British Columbia. He received his M.A.Sc. and B.A.Sc in electrical and computer engineering from University of British Columbia and University of Toronto in 2004 and 2002 respectively. His research interests include high-speed signal integrity issues, jitter measurement, serial communications. Touraj Farahmand received the B.Sc. degree in Electrical Engineering from Esfahan University of Technology, Esfahan, Iran in 1989 and the M.Sc. in Control Engineering from Sharif university of Technology, Tehran, Iran in 1992. After graduation, he joined the Electrical and Computer Research center of Esfahan University of Technology where he was involved in the DSP algorithm development and design and implementation of the control and automation systems. Since October 2001, he has been working in the area of high-speed signal timing measurement at SoC (System-on-a-Chip) lab of UBC (University of British Columbia) as a research engineer. His research interests are signal processing, jitter measurement, serial communication and control. André Ivanov is Professor in the Department of Electrical and Computer Engineering, at the University of British Columbia. Prior to joining UBC in 1989, he received his B.Eng. (Hon.), M. Eng., and Ph.D. degrees in Electrical Engineering from McGill University. In 1995–96, he spent a sabbatical leave at PMC-Sierra, Vancouver, BC. He has held invited Professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, in Perth, Australia. His primary research interests lie in the area of integrated circuit testing, design for testability and built-in self-test, for digital, analog and mixed-signal circuits, and systems on a chip (SoCs). He has published widely in these areas and holds several patents in IC design and test. Besides testing, Ivanov has interests in the design and design methodologies of large and complex integrated circuits and SoCs. Dr. Ivanov has served and continues to serve on numerous national and international steering, program, and/or organization committees in various capacities. Recently, he was the Program Chair of the 2002 VLSI Test Symposium (VTS'02) and the General Chair for VTS'03 and VTS'04. In 2001, Ivanov co-founded Vector 12, a semiconductor IP company. He has published over 100 papers in conference and journals and holds 4 US patents. Ivanov serves on the Editorial Board of the IEEE Design and Test Magazine, and Kluwer's Journal of Electronic Testing: Theory and Applications. Ivanov is currently the Chair of the IEEE Computer Society's Test Technology Technical Council (TTTC). He is a Golden Core Member of the IEEE Computer Society, a Senior Member of the IEEE, a Fellow of the British Columbia Advanced Systems Institute and a Professional Engineer of British Columbia. Yong Cho received the B.S. degree from Kyung Pook National Unviersity, Korea, in 1981 and the M.S. degree from in electrical and computer engineering from the University of South Carolina, Columbia, S.C., in 1988 and the Ph.D. degree in electrical engineering and applied physics from Case Western Reserve University, Cleveland, OH, in 1992. He is currently a Professor with the Department of Electronics Engineering, Konkuk University, Seoul, Korea. His recent research interests include SoC Design and Verification, H/W and S/W co-design, and embedded programming on SoC. Sassan Tabatabaei received his PHD in Electrical Engineering from the University of British Columbia, Vancouver, Canada in 2000. Since then, he has held several senior technical positions at Vector12 Corp, Guide Technology, and Virage Logic. His professional and research interests include mixed-signal design and test, and signal integrity and jitter test methodologies for high-speed circuits and multi-Gbps serial interfaces. He has published several papers and holds a US patent in the area of timing and jitter measurement. Currently, he holds the position of the director for embedded test at Virage Logic Corporation.     

Joseph L. Locicero September 18, 1947 - July 19, 2008

Joseph L. LoCicero was born on September 18, 1947 in the Borough of The Bronx, New York City, New York, USA. He received his academic training at the City College of New York (BSEE 1970 and MSEE 1971) and the City University of New York (Ph.D. 1977). He performed his doctoral thesis research under Donald L. Schilling. Upon receipt of his doctoral degree he joined Illinois Institute of Technology (IIT) as a faculty member in what is now the Electrical and Computer Engineering (ECE) Department, where he served for over 30 years as Assistant Professor, Associate Professor, Professor, and Motorola Chair Professor, as well as undertaking the position of Acting Chair of the ECE Department for two years. He was one of the co-founders of the Wireless Network and Communications (WiNCom) Research Center.     

The effects of synchronization on topology-transparent scheduling

Topology-transparent scheduling is an attractive medium access control technique for mobile ad hoc networks (MANETs) and wireless sensor networks (WSNs). The transmission schedule for each node is fixed and guarantees a bounded delay independent of which nodes are its neighbours, as long as the active neighbourhood is not too dense. Most of the existing work on topology-transparent scheduling assumes that the nodes are synchronized on frame boundaries. Synchronization is a challenging problem in MANETs and in WSNs. Hence, we study the relationships among topology-transparent schedules, expected delay, and maximum delay, for successively weaker models of synchronization: frame-synchronized, slot-synchronized, and asynchronous transmission. For each synchronization model, we give constructive proofs of existence of topology-transparent schedules, and bound the least maximum delay. Perhaps surprisingly, the construction for the asynchronous model is a simple variant of the slot synchronized model. While it is foreseen that the maximum delay increases as the synchronization model is weakened, the bound is too pessimistic. The results on expected delay show that topology-transparent schedules are very robust to node density higher than the construction is designed to support, allowing the nodes to cope well with mobility, and irregularities of their deployment. Wensong Chu received his M.S. in Applied Mathematics from Shanghai Jiao Tong University, China, in 1993; received his M.S. in Computer Networks (Electrical Engineering) from the University of Southern California in 2000; received his Ph.D. in Mathematics from the University of Southern California in 2002. He was with the Department of Computer Science and Engineering at Arizona State University as a post-doctoral fellow from 2002 to 2003. Currently he is doing research at the CMS Bondedge in California. His research interests include sequence designs for communications, combinatorial coding methods, mobile ad hoc networks and sensor networks, financial engineering and combinatorial design theory. Charles J. Colbourn was born in Toronto, Canada in 1953. He completed his B.Sc. degree at the University of Toronto in 1976, M.Math. at the University of Waterloo in 1978, and Ph.D. at the University of Toronto in 1980, all in computer science. He has held faculty positions at the University of Saskatchewan, the University of Waterloo, and the University of Vermont, and is now Professor of Computer Science and Engineering at Arizona State University. He is co-editor of the CRC Handbook of Combinatorial Designs and author of Triple Systems and The Combinatorics of Network Reliability, both from Oxford University Press. He is editor-in-chief of the Journal of Combinatorial Designs. His research concerns applications of combinatorial designs in networking, computing, and communications. Violet R. Syrotiuk earned the Ph.D. degree in Computer Science from the University of Waterloo (Canada) in 1992. She joined Arizona State University in 2002 and is currently an Assistant Professor of Computer Science and Engineering. Dr. Syrotiuk’s research is currently supported by three grants from the National Science Foundation, and contracts from Los Alamos National Laboratory, and the Defence Science and Technology Organisation in Australia. She serves on the Editorial Board of Computer Networks, and on the Technical Program Committee of several major conferences including MobiCom and Infocom. Her research interests include mobile ad hoc and sensor networks, in particular MAC protocols with an emphasis on adaptation, topology-transparency, and energy efficiency, dynamic spectrum utilization, mobile network models, and protocol interaction and cross-layer design. She is a member of the ACM and the IEEE.     

Set of Sequences for QS-CDMA Systems with Multi-User Detection and Multipath-Fading Channels

In this work Walsh–Hadamard, QS, Lin–Chang, LCZ-GMW, ZCZ sets of sequences are compared. The comparison is accomplished by analyzing the conventional receiver (Rake) and a parallel interference canceller (PIC) receiver performance using each one of these sequence sets in a multipath Rayleigh fading channel and similar system loads in quasi-synchronous condition.André Seichi Ribeiro Kuramoto received the B.S. degree in Electrical Engineering from UEL, Londrina State University (Brazil) in 2002. He is currently an M.Sc. student at EPUSP – Escola Politécnica of University of São Paulo (Brazil) and his current research interests are quasi-synchronous DS-CDMA systems and code sequences analysis.Taufik Abrão received the B.S., M.Sc. and Ph.D., all in Electrical Engineering from EPUSP – Escola Politécnica of University São Paulo (Brazil), in 1992, 1996, and 2001, respectively. He is currently an Adjunct Professor at the Electrical Engineering Department of UEL, State University of Londrina (Brazil) and his current research interests are CDMA systems, multi-user detection, and code sequences analysis.Paul Jean Etienne Jeszensky received the B.S., M.S. and Ph.D., all in Electrical Engineering from EPUSP – Escola Politécnica of University of São Paulo (Brazil), in 1972, 1981, and 1989, respectively. Since 1990, he has been with EPUSP where he is a full-time Associate Professor and Researcher in Communication Systems. He was visiting professor at UPC – Universitat Politécnica de Catalunya, Barcelona (Spain) in 1995 and at TUB – Technical University of Budapest (Hungary) in 2001. He is author of the book Sistemas Telefônicos (in Portuguese), Editora Manole, 2003, and his current research interests include CDMA systems, multi-user detection, code sequences analysis and related topics.     

Pipeline of Successive Approximation Converters with Optimum Power Merit Factor

In this paper, we present a low power 12 bit 5 MSPS, successive approximation converter architecture using pipeline technique. The converter consumes 4 mW at the Nyquist rate input with 1.8 V power supply. By combination of pipeline and successive architecture, the entire circuit, simulated at the transistor level in a 0.18 μ CMOS process, achieves a FoM (Figure of Merit) of 0.19 pJ/conversion. Jinghua Li was born in 1973. He received the MSEE and BSEE Degree from College of Electronics and information, Shanghai Jiaotong University and Harbin Engineering University in 1997 and 1994 respectively. He is currently pursuing Ph.D degree in Department of Electrical Engineering, Texas A&M University, College Station, TX, USA. In 1997, he joined Bell Laboratory (China), Lucent Technologies as a member of technical staff. He worked on single-chip HDTV decoder IC and Sonet/SDH SoC for various projects in Murray Hill, NJ, USA and Shanghai China. He also finished projects on hardware implementation of Video conference/Phone based on H.263 standard as his master thesis. Since 2000, he has been a research assistant in Analog Mixed Signal center, TAMU. Most currently his research interests are focused on low power analog to digital conversion IC design, CMOS implementation of 10 G/2.5 G clock data recovery IC for high speed serial communications. Franco Maloberti received the Laurea Degree in Physics (Summa cum Laude) from the University of Parma, Parma Italy, in 1968 and the Dr. Honoris Causa degree in electronics from the Instituto Nacional de Astrofisica, Optica y Electronica (Inaoe), Puebla, Mexico in 1996. In 1993 he was a Visiting Professor at ETH-PEL, Zurich. He was Professor of Microelectronics and Head of the Micro Integrated Systems Group University of Pavia, Pavia, Italy and the TI/J.Kilby Analog Engineering Chair Professor at the Texas A&M University. He is currently the Distinguished Microelectronic Chair Professor at University of Texas at Dallas and part-time Professor at the University of Pavia, Italy. His professional expertise is in the design, analysis and characterization of integrated circuits and analogue digital applications, mainly in the areas of switched capacitor circuits, data converters, interfaces for telecommunication and sensor systems, and CAD for analogue and mixed A-D design. He has written more than 250 published papers, three books and holds 15 patents. He was in 1992 recipient of the XII Pedriali Prize for his technical and scientific contributions to national industrial production. He was co-recipient of the 1996 Institute of Electrical Engineers (U.K.) Fleming Premium for the paper “CMOS Triode Transistor Transconductor for high-frequency continuous time filters.” He has been responsible at both technical and management levels for many research programs including ten ESPRIT projects and has served the European Commission as ESPRIT Projects' Evaluator, Reviewer and as European Union expert in many European Initiatives. He served the Academy of Finland on the assessment of electronic research in Academic institutions and on the research programs' evaluations. Dr. Maloberti was Vice-President, Region 8, of the IEEE Circuit and Systems Society from 1995 to 1997 and an Associate Editor of IEEE-Transaction on Circuit and System-II. He received the 1999 IEEE CAS Society Meritorious Service Award, the 2000 CAS Society Golden Jubilee Medal, and the IEEE Millenium Medal. He is the President of the IEEE Sensor Council and member of the Board of Governors of the IEEE CAS Society. He is a member of the Italian Electrothecnical and Electronic Society (AEI), the Editorial Board of Analog Integrated Circuits and Signal Processing, and Fellow of IEEE.     

A CMOS Image Processing Sensor for the Detection of Image Features

A compact CMOS vision sensor for the detection of higher level image features, such as corners, junctions (T-, X-, Y-type) and linestops, is presented. The on-chip detection of these features significantly reduces the data amount and hence facilitates the subsequent processing of pattern recognition. The sensor performs a series of template matching operations in an analog/digital mixed mode for various kinds of image filtering operations including thinning, orientation decomposition, error correction, set operations, and others. The analog operations are done in the current domain. A design procedure, based on the formulation of the transistor mismatch, is applied to fulfill both accuracy and speed requirements. The architecture resembles a CNN-UM that can be programmed by a 30-bit word. The results of an experimental 16 × 16 pixel chip demonstrate that the sensor is able to detect features at high speed due to the pixel-parallel operation. Over 270 individual processing operations are performed in about 54 μsec. Masatoshi Nishimura was born in 1962 in Japan. He received his B.S. degree in mathematical engineering and information physics from the University of Tokyo in 1984. In 2001 he received his Ph.D. in Electrical Engineering from the University of Pennsylvania. His Ph.D. research focused on biologically inspired algorithms for the feature detection in visual images. Except for the three years he spent at University of Pennsylvania, he has been working for Sankyo since 1984, where he has been involved in the research and development of medical instruments including a microchip for capillary electrophoresis. He is currently working in the field of bioinformatics. Jan Van der Spiegel received his Masters and Ph.D. degrees in Electrical Engineering from the University of Leuven, Belgium, in 1974 and 1979, respectively. He joined the University of Pennsylvania in 1981 where he is currently a Professor of Electrical and Systems Engineering and the director of the Center for Sensor Technologies. He was the chairman of the Department of Electrical Engineering from 1998 to 2002 and the interim chairman of the Electrical and Systems Engineering department at the University of Pennsylvania from 2002 to 2004. His research interests are in mixed-mode VLSI design, biologically based sensors and sensory information processing systems, micro-sensor technology, and analog-to-digital converters. He is the author of over 150 journal and conference papers and holds 4 patents. He is a Fellow of the IEEE (2002) and the recipient of the IEEE Third Millennium Medal, the UPS Foundation Distinguished Education Chair and the Bicentennial Class of 1940 Term Chair. He received the Christian and Mary Lindback Foundation, and the S. Reid Warren Award for Distinguished Teaching. He was also Editor of Sensors and Actuators A for North and South America from 1983 to 2004.