A charge pump for driving CMOS active pixel reset

To overcome the limitation of low image signal swing range and long reset time in four Iransistor CMOS active pixel image sensor, a charge pump circuit is presented to improve the pixel reset performance. The charge pump circuit consists of two stage switch capacitor serial voltage doubler. Cross-coupled MOSFET switch structure with well close and open performance is used in the second stage of the charge pump. The pixel reset transistor with gate voltage driven by output of the pump works in linear region, which can accelerate reset process and complete reset is achieved. The simulation results show that output of the charge pump is enhanced from 1.2 to 4.2 V with voltage ripple lower than 6 inV. The pixel reset time is reduced to 1.14 ns in dark. Image smear due to non-completely reset is elIminated and the image signal swing range is enlarged. The charge pump is successfully embedded in a CMOS image sensor chip with 0.3 × 10^6 pixels.     

Reset noise reduction through column-level feedback reset in CMOS image sensors

A low reset noise CMOS image sensor(CIS) based on column-level feedback reset is proposed.A feedback loop was formed through an amplifier and a switch.A prototype CMOS image sensor was developed with a 0.18μm CIS process.Through matching the noise bandwidth and the bandwidth of the amplifier,with the falling time period of the reset impulse 6μs,experimental results show the reset noise level can experience up to 25 dB reduction.The proposed CMOS image sensor meets the demand of applications in high speed security surveillance systems,especially in low illumination.     

包含交流耦合CTIA与数字CDS的CMOS图像传感器设计

设计了一种带隔直电容的交流耦合CTIA像元电路与数字相关双采样（DCDS）结构的CMOS图像传感器系统。在传统的CTIA像元电路中增加隔直电容,通过控制光电二极管的偏压,达到减小光电二极管暗电流的目的;同时采用片外数字CDS结构,通过在片外实现复位信号与像元积分信号的量化结果在数字域的减法,可以减小图像传感器像元的复位噪声和固定图案噪声（FPN）。基于0.35 m标准CMOS工艺对此CMOS图像传感器进行流片,像元阵列为256256,像元尺寸为16 m16 m。测试结果表明交流耦合CTIA像元电路可以将光电二极管的偏压控制在零偏点附近,此时其暗电流最小;采用了数字CDS结构后,图像传感器像元的时域噪声及固定图案噪声均有不同程度降低。     

CMOS active pixel image sensor with simple floating gate pixels

A new pixel structure using a simple floating gate (SFG) has been proposed. The pixel consists of a coupling capacitor, a photogate, a barrier gate and a MOS transistor. It features complete reset that results in no kTC noise and no image lag, high blooming overload protection, nondestructive readout (NDRO), and CMOS compatibility. Its basic operation has been confirmed with a 32(H)×27(V) pixel area array. Since the pixel structure is relatively simple, small pixel size is feasible     

High speed SOI CMOS image sensor with pinned photodiode on handle wafer

We have fabricated SOI CMOS active pixel image sensor with pinned photodiode on handle wafer. The structure of one pixel is a four-transistor type active pixel image sensor, which consists of a reset and a source follower transistor on seed wafer, and is comprised of a photodiode, a transfer gate, and a floating diffusion on handle wafer. The photodiode could be optimized for better quantum efficiency and low dark currents because the process of a photodiode on handle wafer is independent of that of transistors on seed wafer. Most of the wavelengths are absorbed within the visible range, because the optimized photodiode is located on the handle wafer. The response time of SOI CMOS active pixel sensor was about 2 times faster than that of bulk CMOS active pixel image sensor.     

High-sensitivity and no-crosstalk pixel technology for embeddedCMOS image sensor

A high-photosensitivity and no-crosstalk pixel technology has been developed for an embedded active-pixel CMOS image sensor, by using a 0.35-μm CMOS logic process. To increase the photosensitivity, we developed a deep p-well photodiode and an antireflective film, consisting of Si₃N₄ film, for the photodiode surface. To eliminate the high voltage required for the reset transistor in the pixel, we used a depletion-type transistor as the reset transistor. The reset transistor also operates as an overflow control gate, which enables antiblooming overflow when excess charge is generated in the photodiode by high-illumination conditions. To suppress pixel crosstalk caused by obliquely incident light, a double-metal photoshield was used, while crosstalk caused by electron diffusion in the substrate was suppressed by using the deep p-well photodiode. A 1/3-in 330-k-pixel active-pixel CMOS image sensor was fabricated using this technology. A sensitivity improvement of 110% for 550-nm incident light was obtained by using the deep p-well photodiode, while an improvement of 24% was obtained by using the antireflective film. The pixel crosstalk was suppressed to less than 1% throughout the range of visible light     

Analysis and reduction of signal readout circuitry temporal noisein CMOS image sensors for low-light levels

In this paper, analytical noise analysis of correlated double sampling (CDS) readout circuits used in CMOS active pixel image sensors is presented. Both low-frequency noise and thermal noise are considered. The results allow the computation of the output RMS noise versus MOS transistor dimensions with the help of SPICE-based circuit simulators. The reset noise, the influence of floating diffusion capacitance on output noise and the detector charge-to-voltage conversion gain are also considered. Test circuits were fabricated using a standard 0.7 μm CMOS process to validate the results. The analytical noise analysis in this paper emphasizes the computation of the output variance, and not the output noise spectrum, as more suitable to CDS operation. The theoretical results are compared with the experimental data     

A low-noise low-offset capacitive sensing amplifier for a 50-/spl mu/g//spl radic/Hz monolithic CMOS MEMS accelerometer

This paper describes a CMOS capacitive sensing amplifier for a monolithic MEMS accelerometer fabricated by post-CMOS surface micromachining. This chopper stabilized amplifier employs capacitance matching with optimal transistor sizing to minimize sensor noise floor. Offsets due to sensor and circuit are reduced by ac offset calibration and dc offset cancellation based on a differential difference amplifier (DDA). Low-duty-cycle periodic reset is used to establish robust dc bias at the sensing electrodes with low noise. This work shows that continuous-time voltage sensing can achieve lower noise than switched-capacitor charge integration for sensing ultra-small capacitance changes. A prototype accelerometer integrated with this circuit achieves 50-/spl mu/g//spl radic/Hz acceleration noise floor and 0.02-aF//spl radic/Hz capacitance noise floor while chopped at 1 MHz.     

Noise in a CMOS digital pixel sensor

Based on the study of noise performance in CMOS digital pixel sensor(DPS),a mathematical model of noise is established with the pulse-width-modulation(PWM) principle.Compared with traditional CMOS image sensors,the integration time is different and A/D conversion is implemented in each PWM DPS pixel.Then,the quantitative calculating formula of system noise is derived.It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region. In this model,photodiode shot noise does not vary with luminance,but dark current shot noise does.According to increasing photodiode capacitance and the comparator’s reference voltage or optimizing the mismatch in the comparator,the total noise can be reduced.These results serve as a guideline for the design of PWM DPS.     

An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor

An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor is presented.This new approach is based on the assumption that the photon shot noise in image signal is impacted by a potential well structure change of pixel.Experimental results show the measured pinch-off voltage is consistent with theoretical prediction.This technique provides an experimental method to assist the optimization of pixel design in both the photodiode structure and fabrication process for the 4-T CMOS image sen...     

CMOS有源像素传感器像素级噪声的分析与抑制

像素级的噪声是CMOS图像传感器的主要噪声源之一。针对CMOS有源像素传感器3T结构像素级的噪声问题,分析了3种抑制像素级噪声的方法。分析结果表明,复位晶体管的软复位噪声要小于硬复位噪声的2倍,PMOS管的1/f噪声低于NMOS管的1/f噪声,同时1/f噪声会随着栅面积的减小而增大。通过对像素的噪声分析,完成了3种像素级的集成电路的设计仿真,并采用了0.5μm标准CMOS工艺进行流片制作。测试表明,噪声的相对变化与分析结果吻合。     

一种获得四管CMOS图像传感器像素夹断电压的方法

提出了一种测试四管CMOS图像传感器像素夹断电压的方法。该方法是基于像素中势阱结构的变化能够对图像信号散粒噪声产生影响的假设。实验结果测得的夹断电压与理论预测相一致。该技术提供的实验方法不仅能够帮助设计四管CMOS图像传感器光电二极管的结构,而且也能优化像素生产工艺。     

Low-power reduced transistor image sensor

An image sensor comprising an array of 128 by 50 super pixels, column parallel current conveyors and global difference double sampling (DDS) unit is presented. The super pixel consists of: a reset transistor, a readout transistor, four transfer transistors and four photodiodes. The photo pixel address switch is placed outside the pixel, effectively implementing 1.5 transistors per pixel using a sharing scheme of the readout and reset transistor. The column FPN of 0.43% from saturated level and SNR of 43.9 dB is measured. The total power consumption is 5 mW at 30 frame/s.     

CMOS数字像素传感器噪声研究

在研究CMOS数字像素传感器(DPS)噪声特性的基础上,利用脉冲宽度调制(PWM)原理建立了关于PWM DPS完善的系统噪声数学模型。相比于传统CMOS图像传感器噪声研究,该模型考虑了系统中各像素单元积分时间不同和像素级模数转换的特点,推导出总噪声表达式。研究表明,低照度时噪声由暗电流散粒噪声主导,光强大时主要来源为光电二极管散粒噪声。模型中光电二极管散粒噪声与光照无关、暗电流散粒噪声与光照有关。研究结果表明针对PWM DPS系统,适当增大节点电容和比较器参考电压、改善比较器失配可有效降低噪声。     

Total dose radiation effects of hybrid bulk/SOI CMOS active pixel with buried channel SOI source follower

A CMOS active pixel with pinned photodiode which used in-pixel buried-channel (BC) transistor has been reported, and the characteristic of CMOS image sensor with in-pixel buried-channel transistor was carried out. In this paper, we have a research on a hybrid bulk/silicon-on-insulator (SOI) CMOS active pixel with pinned photodiode which use buried channel SOI NMOS Source Flower (SF) by simulation. We study the basic characteristics of buried-channel SOI NMOS and the characteristics of CMOS active pixel optimized by using in-pixel buried-channel SOI transistor under radiation. The results show that, compared to the conventional active pixel with the standard surface-channel (SC) SOI NMOS SF, the dark random noise of the pixel which uses in-pixel buried channel SOI NMOS SF can be reduced under the radiation and the output swing is improved.     

Operation Principles of 0.18-$muhboxm$Four-Transistor CMOS Image Pixels With a Nonfully Depleted Pinned Photodiode

The operation principles of the four-transistor (4-TR) pixel CMOS image sensor, fabricated by 0.18-mum technology, were investigated by pixel-level characterization utilizing a single-pixel test pattern. It was found that the pixel's dark current level is strongly influenced by the gate bias (V_TX(on)) of the transfer (TX) transistor at a fixed supply voltage (V_DD). The largest dark current occurred at a conventional bias condition of V_TX(on)=V_DD=2.5V, but the dark current level was reduced by less than one-third at V_TX(on)=2.1V without degrading the pixel's charge transfer capabilities. Attributed to the dark current reduction, the fixed-pattern noise (FPN) of pixel was also decreased by up to 13.3 dB. These improvements can be explained by the more effective reset of pinned photodiode (PPD) at V_TX(on)=2.1V, especially in the pixel with V_DD of 2.5 V or lower in which the full depletion of PPD becomes more and more difficult. In this bias condition, namely nonfully depletion PPD condition, the TX transistor was proven to operate in the "deepest depletion" mode by effectively suppressing the electron injection from floating diffusion node to channel. Moreover, various driving signals to the TX transistor were applied to do more detailed physical analysis of the pixel operation. Since the dark current and FPN are main bottlenecks in most CMOS image sensors, the proposed method is expected to efficiently improve the performance of 4-TR CMOS image pixels under 2.5 V or lower operational voltages     

8.9-Megapixel Video Image Sensor With 14-b Column-Parallel SA-ADC

An 8.9-megapixel 60-frames/s video image sensor with a 14-b column-parallel analog-to-digital converter (ADC) has been developed. A gain amplifier, a 14-b successive approximation ADC (SA-ADC), and a new column digital processor are employed in each column. The SA-ADC has sufficient operation speed to convert the pixel reset and the pixel signal into digital data in a row operation cycle. The column digital processor receives bit serial data from the SA-ADC output and performs subtraction of the reset data from the signal data in order to reduce column fixed pattern noise (FPN). Column FPN is successfully reduced to 0.36 e_rms ^- by this digital-domain column FPN correction. Low-voltage low-power serial video interface and noise decoupling on pixel drive voltages contribute to row-temporal-noise reduction to 0.31 e_rms ^-. Both column FPN and row temporal noise are not visible in spite of a low readout noise floor of 2.8 e_rms ^-.     

A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters

This paper presents a high-speed, high-sensitivity 512times512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a charge amplifier for high charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm ² are integrated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-mum CMOS image sensor technology achieves the full frame rate in excess of 3500 frames/s. The in-pixel charge amplifier achieves the optical sensitivity of 19.9 V/lxmiddots. The signal full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8mV_rms, and the resulting signal dynamic range is 60 dB     

低照度CMOS图像传感器设计与实现

设计了一种基于电容反馈跨阻放大器型（Capacitive Trans-impedance Amplifier,CTIA）像元电路与双采样（Delta Double Sampling,DDS）的低照度CMOS图像传感器系统。采用CTIA像元电路提供稳定的光电二极管偏置电压以及高注入效率,完成在低照度情况下对微弱信号的读取;同时采用数字DDS结构,通过在片外实现像元积分信号与复位信号的量化结果在数字域的减法,达到抑制CMOS图像传感器中固定图案噪声的目的,进一步提高低照度CIS的成像质量。基于0.35 m标准CMOS工艺对此基于CTIA像元电路的CMOS图像传感器芯片进行流片,像元阵列为256256,像元尺寸为16 m16 m。测试结果表明该低照度CMOS图像传感器系统可探测到0.05 lx光照条件下的信号。     

Design and evaluation of current-mode image sensors in CMOS-technology

Three different current-mode-output CMOS image sensor structures comprising of a pixel cell and an appropriate readout circuit have been analyzed and compared with regard to their noise behavior, fixed-pattern noise (FPN), and the dynamic range. First, a standard integrating pixel cell with a readout circuit containing a voltage-to-current converter is proposed. Second, a pixel cell based on a switched current cell is analyzed. The third sensor cell uses a feedback loop to control the reverse bias voltage of the photodiode to reduce the settling time of the pixel cell and the influence of the photodiodes's dark current. The necessary amplifier is partly located in the pixel cell and partly in the readout circuit. In all sensors, correlated double sampling is used to suppress the FPN.