CMOS数字像素传感器噪声研究

在研究CMOS数字像素传感器(DPS)噪声特性的基础上,利用脉冲宽度调制(PWM)原理建立了关于PWM DPS完善的系统噪声数学模型。相比于传统CMOS图像传感器噪声研究,该模型考虑了系统中各像素单元积分时间不同和像素级模数转换的特点,推导出总噪声表达式。研究表明,低照度时噪声由暗电流散粒噪声主导,光强大时主要来源为光电二极管散粒噪声。模型中光电二极管散粒噪声与光照无关、暗电流散粒噪声与光照有关。研究结果表明针对PWM DPS系统,适当增大节点电容和比较器参考电压、改善比较器失配可有效降低噪声。     

An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor

An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor is presented.This new approach is based on the assumption that the photon shot noise in image signal is impacted by a potential well structure change of pixel.Experimental results show the measured pinch-off voltage is consistent with theoretical prediction.This technique provides an experimental method to assist the optimization of pixel design in both the photodiode structure and fabrication process for the 4-T CMOS image sen...     

一种获得四管CMOS图像传感器像素夹断电压的方法

提出了一种测试四管CMOS图像传感器像素夹断电压的方法。该方法是基于像素中势阱结构的变化能够对图像信号散粒噪声产生影响的假设。实验结果测得的夹断电压与理论预测相一致。该技术提供的实验方法不仅能够帮助设计四管CMOS图像传感器光电二极管的结构,而且也能优化像素生产工艺。     

CMOS图像传感器固定模式噪声抑制新技术。

针对有源像素(APS)CMOS图像传感器中的固定模式噪声(FPN),设计了一种动态数字双采样的噪声抑制新技术;该技术比普通双采样技术具有更佳的抑制效果,其电路结构简单,适合于像素尺寸不断缩小的CMOS图像传感器发展趋势。通过MPW计划,采用Chartered0.35μmCMOS工艺制作了测试ASIC芯片,试验结果表明动态数字双采样技术有效抑制了FPN噪声。     

A time error model for time-based PWM pixel with correlated double sample in the circumstance of nonlinear response

A time error mathematical model is proposed to study the impact of nonlinear response and noises on imaging of time-based Pulse Width Modulation (PWM) pixel with the Correlated Double Sampling (CDS). The errors introduced by nonlinearity and certain noises, including fixed pattern noise (FPN), reset noise, shot noise and input-referred noise of pixel-level comparator, are studied. The relative error is impacted not only by the noise voltage, but also the comparator reference voltages, V_refh and V_refl. In the 0.18 μm CMOS process, the simulation result shows that the noises which have the largest impact on imaging are FPN and shot noise. The higher the V_refh and V_refl are, the smaller the error is introduced by FPN. The larger the difference between V_refh and V_refl is, the better the signal-to-noise ratio (SNR) is. The influence of reference voltage and clock frequency on dynamic range, and the trade-off between dynamic range and speed are also analyzed in this paper. Finally, the rules of reference voltage selection are discussed. The results can serve as a guideline to the design of the time-based PWM pixel with CDS.     

低噪声CMOS图像传感器技术研究综述

文章总结了低噪声CMOS图像传感器代表性关键技术的最新研究进展。从CMOS图像传感器架构及各模块设计的角度,介绍了有源像素结构和图像传感器架构,分析了广泛采用的像素内源跟随CMOS图像传感器读出电路及其噪声等效模型,重点介绍了低噪声CMOS图像传感器关键技术,包括共享参考像素差分共源放大器技术、相关多采样技术、像素内斩波技术,以及相关技术的电路级实现方式。     

CMOS有源像素传感器像素级噪声的分析与抑制

像素级的噪声是CMOS图像传感器的主要噪声源之一。针对CMOS有源像素传感器3T结构像素级的噪声问题,分析了3种抑制像素级噪声的方法。分析结果表明,复位晶体管的软复位噪声要小于硬复位噪声的2倍,PMOS管的1/f噪声低于NMOS管的1/f噪声,同时1/f噪声会随着栅面积的减小而增大。通过对像素的噪声分析,完成了3种像素级的集成电路的设计仿真,并采用了0.5μm标准CMOS工艺进行流片制作。测试表明,噪声的相对变化与分析结果吻合。     

A Sub-$muhbox{W}$ Fully Tunable CMOS DPS for Uncooled Infrared Fast Imaging

This paper presents a very low-power and fully programmable CMOS digital active pixel sensor for uncooled IR fast imaging. The proposed circuit topology includes self-biasing, built-in input capacitance compensation, predictive A/D conversion, and a truly digital I/O interface, all at pixel level. Furthermore, full fixed pattern noise cancellation is also supplied by the external digital tuning of both offset and gain for each individual pixel at no speed costs. Two DPS circuit implementations for IR PbSe sensors have been integrated in standard 0.35-$mu{hbox {m}}$ 2-polySi 4-metal CMOS technology. Finally, exhaustive experimental results from their electrical tests are reported to validate the proposed DPS design techniques.      

Analysis of temporal noise in CMOS photodiode active pixel sensor

Temporal noise sets the fundamental limit on image sensor performance, especially under low illumination and in video applications. In a CCD image sensor, temporal noise is primarily due to the photodetector shot noise and the output amplifier thermal and 1/f noise. CMOS image sensors suffer from higher noise than CCDs due to the additional pixel and column amplifier transistor thermal and 1/f noise. Noise analysis is further complicated by the time-varying circuit models, the fact that the reset transistor operates in subthreshold during reset, and the nonlinearity of the charge to voltage conversion, which is becoming more pronounced as CMOS technology scales. The paper presents a detailed and rigorous analysis of temporal noise due to thermal and shot noise sources in CMOS active pixel sensor (APS) that takes into consideration these complicating factors. Performing time-domain analysis, instead of the more traditional frequency-domain analysis, we find that the reset noise power due to thermal noise is at most half of its commonly quoted kT/C value. This result is corroborated by several published experimental data including data presented in this paper. The lower reset noise, however, comes at the expense of image lag. We find that alternative reset methods such as overdriving the reset transistor gate or using a pMOS transistor can alleviate lag, but at the expense of doubling the reset noise power. We propose a new reset method that alleviates lag without increasing reset noise     

一种具有高填充因数和动态数字双采样技术的CMOS图像传感器

介绍了基于0.35μm工艺设计的单片CMOS图像传感器芯片.该芯片采用有源像素结构,像素单元填充因数可达到43%,高于通常APS结构像素单元30%的指标.此外还设计了一种数字动态双采样技术,相对于传统的双采样技术(固定模式噪声约为0.5%),数字动态双采样技术具有更简洁的电路结构和更好抑制FPN噪声的效果.传感器芯片通过MPW计划采用Chartered 0.35μm数模混合工艺实现.实验结果表明芯片工作良好,图像固定模式噪声约为0.17%.     

有源像素传感器恒星探测极限计算方法

恒星探测极限是星跟踪器的一个关键参数，在导航星库的建立和星图识别过程中起着重要作用。根据恒星辐射模型和CMOS有源像素传感器的噪声计算模型，提出了一种在给定信噪比和有源像素传感器噪声条件下，计算星跟踪器恒星探测极限的方法。该方法利用单位时间内、单位面积上有源像素传感器对0星等恒星的响应来求取恒星探测极限。最后，在信噪比为8的条件下，结合星跟踪器的有关参数给出了一个计算恒星探测极限的具体实例。     

Novel color demosaicking for noisy color filter array data

Single sensor digital color still/video cameras use color demosaicking to reproduce full color images from color filter array (CFA) data. The quality of interpolated image will be degraded due to the sensor noise introduced during the image capture process. Many conventional demosaicking-denoising solutions adopt the channel-dependent noise model, which may fit the CMOS/CCD image sensor less than signal-dependent noise model. In this paper, the wavelet sub-band decomposition and synthesis are applied to interpolate the CFA data with signal-dependent noise model. The major contributions of this work include: (1) The combination of LMMSE and statistical calculation in wavelet domain are utilized to suppress the signal-dependent noise, which is separated into additive noise and multiplicative noise. (2) In CFA data, it has been verified that the quantitative relationship between the current pixel and the adjacent pixel, which locate in the same edge. Both simulated and real CFA images are employed to compare the proposed algorithm with the state-of-the-art techniques reported in the literature. The experimental results confirm that our method outperforms them both on demosaicking performance and on computational cost, when they process the noisy color filter array data.     

Total dose radiation effects of hybrid bulk/SOI CMOS active pixel with buried channel SOI source follower

A CMOS active pixel with pinned photodiode which used in-pixel buried-channel (BC) transistor has been reported, and the characteristic of CMOS image sensor with in-pixel buried-channel transistor was carried out. In this paper, we have a research on a hybrid bulk/silicon-on-insulator (SOI) CMOS active pixel with pinned photodiode which use buried channel SOI NMOS Source Flower (SF) by simulation. We study the basic characteristics of buried-channel SOI NMOS and the characteristics of CMOS active pixel optimized by using in-pixel buried-channel SOI transistor under radiation. The results show that, compared to the conventional active pixel with the standard surface-channel (SC) SOI NMOS SF, the dark random noise of the pixel which uses in-pixel buried channel SOI NMOS SF can be reduced under the radiation and the output swing is improved.     

基于CMOS集成有源传感器的 新型高能物理粒子轨迹追踪器

本文研究了一个采用标准0.35μm CMOS 工艺制造的新型高能物理粒子轨迹追踪器.这个新型的追踪器运用CMOS有源像素传感器技术(CMOS Monolithic Active Pixel Sensors,MAPS)将信号的探测与处理电路集成在一起,在像素的内部实现了相关双次采样操作(Correlated Doubled Sampling,CDS).实验芯片包含一个128行×32列的像素矩阵,其中,像素的大小为25×25μm².通过采用放射源⁵⁵Fe的测定, 得到像素的等效输入随机噪声 (Temporal Noise) 仅为12个电子而固定噪声(Fixed Pattern Noise,FPN)仅为4个电子.传感器的电荷-电压转换系数(Charge-to-Voltage conversion Factor,CVF)为60μV/e^-.测试中,芯片的信号读取速度达到了12μs/帧.     

A DPS array with programmable resolution and reconfigurable conversion time

A CMOS digital pixel sensor (DPS) with programmable resolution and reconfigurable conversion time is described. The chip features a unique architecture based on the pulse width modulation (PWM) technique and operates with either an 8-b or 4-b accuracy. The 8-b conversion mode is used for high-precision imaging while the 4-b conversion mode provides a shorter conversion time and a two times increase in spatial resolution. Two quantization schemes are studied, namely, the uniform and the nonuniform time-domain quantizers, which are referred to as UQ and NUQ, respectively. It is shown that the latter scheme not only permits to linearize the nonlinear response of the PWM sensor, but also allows to significantly speed up the conversion time, particularly for wide dynamic range and low coding resolutions. A prototype of 32/spl times/32/64/spl times/32 pixels has been fabricated using 1-poly, 5-metal CMOS 0.35-/spl mu/m n-well standard process. Power dissipation is 10 mW at V/sub DD/=3.3 V, dynamic range is 90 dB, while dark current was measured at 1 pA. The reconfiguration features of the chip have been verified experimentally.     

320×240 Pixels CMOS Digital Image Sensor with Wide Dynamic Range

A 320×240 CMOS image sensor is demonstrated,which is implemented by a standard 0.6 μm 2P2M CMOS process.For reducing the chip area,each 2×2-pixel block shares a sample/hold circuit,analog-to-digital converter and 1-b memory.The 2×2 pixel pitch has an area of 40 μm×40 μm and the fill factor is about 16%.While operating at a low frame rate,the sensor dissipates a very low power by power-management circuit making pixel-level comparators in an idle state.A digital correlated double sampling,which eliminates fixed pattern noise,improves SNR of the sensor, and multiple sampling operations make the sensor have a wide dynamic range.     

一种6T像素全局曝光CMOS图像传感器

提出了一种基于6T像素结构的全局曝光CMOS图像传感器。通过采用PPD结构的6T像素、高复位电平和低阈值器件,提高了动态范围,并优化设计了像素单元的版图,使之获得较高的填充系数;模拟读出电路部分,通过采用双采样、增益放大和减小列级固定模式噪声(FPN)处理,以及对列选控制电路进行优化,减小了对全局PGA的运放设计要求。芯片的工作频率为20MHz,动态范围为66dB,实现了全局曝光方式CMOS图像传感器的设计。     

Research on Column FPN and Black Level Calibration in Large Array CMOS Image Sensor

A technical investigation, research and im-plementation is presented to correct column fixed pattern noise and black level in large array Complementary metal oxide semiconductor (CMOS) image sensor. Through making a comparison among reported solution, and give large array CMOS image sensor design and considerations, according to our previous analysis on non-ideal factor and error source of piecewise Digital to analog converter (DAC) in multi-channels, an improving accurate piecewise DAC with adaptive switch technique is developed. The research theory has verified by a high dynamic range and low column Fixed pattern noise (FPN) CMOS image sensor prototype chip, which consisting of 8320×8320 pixel array was designed and fabricated in 55nm CMOS 1P4M standard process. The chip active area is 48mm×48mm with a pixel size of 5.7μm×5.7μm. The measured results achieved a high intrinsic dynamic range of 75dB, a low FPN and black level of 0.06％, a low photo response non-uniformity of 1.5％ respectively, and an excellent raw sample image taken by the prototype sensor.     

A digital pixel sensor array with programmable dynamic range

This paper presents a digital pixel sensor (DPS) array employing a time domain analogue-to-digital conversion (ADC) technique featuring adaptive dynamic range and programmable pixel response. The digital pixel comprises a photodiode, a voltage comparator, and an 8-bit static memory. The conversion characteristics of the ADC are determined by an array-based digital control circuit, which linearizes the pixel response, and sets the conversion range. The ADC response is adapted to different lighting conditions by setting a single clock frequency. Dynamic range compression was also experimentally demonstrated. This clearly shows the potential of the proposed technique in overcoming the limited dynamic range typically imposed by the number of bits in a DPS. A 64 /spl times/ 64 pixel array prototype was manufactured in a 0.35-/spl mu/m, five-metal, single poly, CMOS process. Measurement results indicate a 100 dB dynamic range, a 41-s mean dark time and an average current of 1.6 /spl mu/A per DPS.     

基于4T像素结构的CMOS图像传感器设计

传统的CMOS图像传感器采用3T像素结构,但由于自身结构的关系,整体性能难以满足较高的要求,4T像素结构应运而生,它比3T像素有更小的噪声,更好的性能;同时要求控制部分更加复杂。文中介绍了基于一种4T像素结构的图像传感器的设计。