使用非对称内表面氧化层的MOS管性能优化

提出了一种用来提高短沟道MOS管性能的非对称内表面氧化层结构。该结构是在MOS管的源端附近生长一层厚的内表面氧化层,以抑制载流子迁移率的降低,同时,在MOS管的漏端附近生长一层薄的内表面氧化层,以抑制器件的短沟道效应。使用TCAD软件进行仿真和分析,结果显示,与对称内表面氧化层结构相比,非对称内表面氧化层结构具有更好的导通-关断特性。对器件进行优化,当源端较厚的内表面氧化层占总氧化层的比例为15%左右时,器件的性能得到最大幅度的提高。在相同的关断电流下,与对称内表面氧化层器件相比,非对称内表面氧化层器件的导通电流提高5%~15%。     

集成电路中MOS管导通电阻测量方法

MOS管是一种常见的半导体功率器件,随着半导体产业的不断发展和进步,MOS管的各方面性能也得到大幅度的提高,被广泛应用于开关电源、节能灯、电源转换和电源控制等领域。在功率电路中,MOS作为一种多子功率开关器件,其导通电阻是至关重要的参数之一,会影响到应用电路的稳定性和功耗。因此在集成电路测试中对于MOS管导通电阻的精确测量显得尤为重要。对于MOS管导通电阻的测量做了详细分析,并介绍了两种可以准确测量MOS管导通电阻的方法。     

埋部分P+层背栅SOI高压器件新结构

提出了一种埋部分P+层的背栅SOI(Buried Partial P+ layer SOI,BPP+SOI)高压器件新结构.部分P+层的引入不仅有效地增强了源端埋氧层电场,而且还降低了源端PN结表面电场,使器件击穿电压随背栅压的增加而大幅增加,比导通电阻也显著降低.仿真结果表明,在漂移区长度为150μm,背栅压为650V时,BPP+SOI的耐压较常规结构提高了84.9%;在漂移区为120μm,耐压相同的情况下,BPP+SOI的比导通电阻较常规结构降低了31%.     

非对称LDD新结构

本文介绍一种用于超大规模集成电路的最新非对称轻掺杂漏（LDD）结构。该结构采用液相选择氧化物淀积技术和离子注入技术。在MOS晶体管的漏端形成轻掺杂的N-或P-区。使LDD结构源端串联电阻大大减小。这种新结构MOS晶体管（W／L=50μm／0．35μm）导通电流增加，饱和漏电流增加45％。封装密度提高。液相选择氧化物在室温下生成。通过抗蚀剂掩膜实现选择性生长。淀积速率及SiO2颗粒可控性好。非对称LDD结构是VLSI技术的重要发展。     

DPRM工艺中刻蚀工艺关键参数对N/P型MOS管交界处的影响

短沟道效应对器件性能的影响不可忽略,高k/金属栅极(High-k/Metal Gate,HKMG)器件可以很好地抑制短沟道效应。HKMG器件中金属栅极的制备工艺有前栅极制造工艺和后栅极制造工艺,其中虚拟栅去除(Dummy Poly Removal,DPRM)过程是后栅极制造中一道至关重要的制程。由于P型MOS管和N型MOS管的金属栅极填充材料不同,制造工艺中要先完成一种MOS管金属栅极的制作再进行另一种MOS管金属栅极的制作,DPRM后N型MOS管和P型MOS管交界处的结构形貌会直接影响金属栅极的填充,进而影响器件性能。在电子回旋共振刻蚀等离子体源条件下,探究DPRM工艺中过刻蚀过程的关键参数对NMOS管和PMOS管交界处结构形貌的影响,进而总结出减弱N/P型MOS管交界处侧向凹陷程度的工艺条件。     

具有L型栅极场板的双槽双栅绝缘体上硅器件新结构

为了降低绝缘体上硅（SOI）功率器件的比导通电阻,同时提高击穿电压,利用场板（FP）技术,提出了一种具有L型栅极场板的双槽双栅SOI器件新结构.在双槽结构的基础上,在氧化槽中形成第二栅极,并延伸形成L型栅极场板.漂移区引入的氧化槽折叠了漂移区长度,提高了击穿电压;对称的双栅结构形成双导电沟道,加宽了电流纵向传输面积,使比导通电阻显著降低;L型场板对漂移区电场进行重塑,使漂移区浓度大幅度增加,比导通电阻进一步降低.仿真结果表明：在保证最高优值条件下,相比传统SOI结构,器件尺寸相同时,新结构的击穿电压提高了123%,比导通电阻降低了32%;击穿电压相同时,新结构的比导通电阻降低了87.5%;相比双槽SOI结构,器件尺寸相同时,新结构不仅保持了双槽结构的高压特性,而且比导通电阻降低了46%.     

基于不同AlN钝化层的极性GaN MOS器件界面特性

界面质量是影响GaN MOS器件性能以及可靠性的主要因素之一,Al203栅介质与极性GaN界面间插入超薄非晶AlN作为钝化层可以有效改善GaN栅界面特性,针对AIN钝化层生长方式研究了GaN界面优化特性.通过GaN MOS电容的C-V和J-V特性,结合透射电子显微镜(TEM)表征分析,对比了不同生长条件的AlN插入层对GaN MOS电容的界面特性的影响.相比常规热生长AlN钝化层制备的样品,以等离子体NH3为N源在300℃下生长AlN钝化层制备的GaN MOS电容的频散和滞回特性均得到显著改善,界面态密度也略有改善.分析认为,经过等离子体NH3的轰击作用有效地抑制了GaN表面上Ga-O键的形成,在GaN表面直接生长AlN,从而改善了界面特性.     

CoolMOS导通电阻分析及与VDMOS的比较

为了克服传统功率MOS导通电阻与击穿电压之间的矛盾,提出了一种新的理想器件结构,称为超级结器件或CoolMOS,CoolMOS由一系列的P型和N型半导体薄层交替排列组成.在截止态时,由于p型和n型层中的耗尽区电场产生相互补偿效应,使p型和n型层的掺杂浓度可以做的很高而不会引起器件击穿电压的下降.导通时,这种高浓度的掺杂使器件的导通电阻明显降低.由于CoolMOS的这种独特器件结构,使它的电性能优于传统功率MOS.本文对CoolMOS导通电阻与击穿电压关系的理论计算表明,对CoolMOS横向器件:Ron·A=C·V2B,对纵向器件:Ron·A=C·VB,与纵向DMOS导通电阻与击穿电压之间Ron·A=C·V2.5B的关系相比,CoolMOS的导通电阻降低了约两个数量级.     

提高MOS功率晶体管封装可靠性技术研究

功率MOS晶体管的正向导通电阻是器件的重要指标,严重影响器件的使用可靠性。从封装材料、封装工艺等方面论述功率MOS管降低导通电阻、控制空洞、提高器件可靠性的封装技术,并通过一些实例来阐述工艺控制的效果。     

非对称轻掺杂漏(LDD)MOSFET

提出并制作了一种仅有漏端轻掺杂区的MOSFET新结构──非对称LDD MOSFET。它与通常LDD MOSFET相比,抑制热载流子效应的能力相同,源漏串联电阻降低40％左右,线性区和饱和区的跨导分别增加50％和20％左右。用该器件制作的CMOS电路,其速度性能优于通常LDD MOSFET制作的同样电路。     

Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET

In this work, we have studied gate length (L_gate) scalability of Si_0.55Ge_0.45 Implant Free Quantum Well (IFQW) pFET with raised and embedded Si_0.75Ge_0.25 source/drain structures. Although embedded SiGe device shows higher I_dsat which can be attributed to thinner T_inv (more scavenging of High-k interfacial layer), raised SiGe device has better short channel control than embedded SiGe device thanks to shallower junction depth. Raised SiGe device can scale down L_gate by 4 nm compared to embedded SiGe device while maintaining identical I_off. This results in superior intrinsic delay in raised SiGe device.     

新型无结型晶体管特性仿真及性能优化设计

随着晶体管特征尺寸缩小至10 nm以下,传统Si基MOSFET面临诸多挑战,而新型沟道材料和器件结构将有望进一步提升器件性能。基于绝缘体上锗衬底的无结型晶体管(GOI-JLT)制作工艺简单、电学特性优良,有望在空间电子系统中应用。利用TCAD仿真软件Sentaurus,研究了GOI-JLT的电学特性,提出一种通过调节沟道掺杂分布来优化器件性能的方法。仿真结果表明,沟道采用高斯掺杂分布,能显著降低器件关态漏电流(降低约三个数量级),提高开关比(提高约三个数量级),抑制短沟道效应。     

Novel attributes in scaling issues of carbon nanotube field-effect transistors

For the first time, we present a scaling study of carbon nanotube field-effect transistors (CNTFETs) using a two-dimensional model. We investigate the scaling issues in device performance focusing on transconductance characteristics, output characteristics, average velocity, I_on/I_off ratio, subthreshold swing and drain-induced barrier lowering (DIBL) with different gate oxide thicknesses and carbon nanotube (CNT) diameters. We concluded that the I_on/I_off ratio increases with the gate oxide thickness reduction and increase in the CNT diameter and lead to a high on-state current. Furthermore, leakage current reduces with decrease in the gate oxide thickness, but it becomes higher in CNTFETs with larger CNT diameter. Also, our results show the output conductance, transconductance, voltage gain and average electron velocity at the top of the barrier improve in CNTFETs with thinner gate oxide and larger CNT diameter. In addition, the investigation of short channel effects shows that CNTFETs with thinner gate oxide offer lower DIBL and subthreshold swing, but in the CNTFETs with larger CNT diameter DIBL and subthreshold swing become worse.     

Improved Electrical Performance and Reliability of Poly-Si TFTs Fabricated by Drive-In Nickel-Induced Crystallization with Chemical Oxide Layer

Ni-metal-induced crystallization (MIC) of amorphous Si (α-Si) has been employed to fabricate low-temperature polycrystalline silicon thin-film transistors (TFTs). However, the Ni residues degrade the device performance. In this study, a new method for manufacturing MIC–TFTs using drive-in Ni-induced crystallization with a chemical oxide layer (DICC) is proposed. Compared with that of MIC–TFTs, the on/off current ratio (I _on/I _off) of DICC–TFTs was increased by a factor of 9.7 from 9.21 × 10⁴ to 8.94 × 10⁵. The leakage current (I _off) of DICC–TFTs was 4.06 pA/μm, which was much lower than that of the MIC–TFTs (19.20 pA/μm). DICC–TFTs also possess high immunity against hot-carrier stress and thereby exhibit good reliability.     

Sputtered oxides used for passivation layers of amorphous InGaZnO thin film transistors

Four sputtered oxide films (SiO₂, Al₂O₃, Y₂O₃ and TiO₂) along with their passivating amorphous InGaZnO thin film transistors (a-IGZO TFTs) were comparatively studied in this paper. The device passivated by an Al₂O₃ thin film showed both satisfactory performance (μ_FE=5.3 cm²/V s, I_on/I_off>10⁷) and stability, as was probably related to smooth surface of Al₂O₃ thin films. Although the performance of the a-IGZO TFTs with a TiO₂ passivation layer was also good enough (μ_FE=3.5 cm²/V s, I_on/I_off>10⁷), apparent V_th shift occurred in positive bias-stress tests due to the abnormal interface state between IGZO and TiO₂ thin films. Sputtered Y₂O₃ was proved no potential for passivation layers of a-IGZO TFTs in this study. Despite unsatisfactory performance of the corresponding a-IGZO TFT devices, sputtered SiO₂ passivation layer might still be preferred for its high deposition rate and excellent transparency which benefit the mass production of flat panel displays, especially active-matrix liquid crystal displays.     

High-Efficiency All-Small-Molecule Organic Solar Cells Based on New Molecule Donors with Conjugated Symmetric/Asymmetric Hybrid Cyclopentyl-Hexyl Side Chains

All small molecule organic solar cells (ASM-OSCs) have numerous advantages but lower power conversion efficiencies (PCEs) than their polymer equivalents, which is largely due to the suboptimal nanoscale network structure in a bulk heterojunction (BHJ). Herein, new small molecule donors with symmetric/asymmetric hybrid cyclopentyl-hexyl side chains are designed, accounting for manipulated intermolecular interactions and BHJ morphology. Theoretical and experimental results reveal that the asymmetric cyclopentyl-hexyl side chains modification has a significant influence on potential energy surface and intermolecular interaction that can ensure preferable molecular assembly and regulate the D/A interfacial energetics, thus boosting the exciton dissociation and charge transport when pairing with a wide-used acceptor L8-BO. Concurrently, a nanoscale bicontinuous interpenetrating network with optimal domain size can be fully evolved in the BHJ layer. As a consequence, the As-TCp-based binary device achieves a superior PCE of 16.46% in comparison to that of the controlled symmetric counterparts S-BF (14.92%) and A-TCp (15.77%), and ranks one of best performance among ASM-OSCs. This study demonstrates that precise manipulation of the cyclo-alkyl chain in combination with the asymmetric 2D side chain strategy is an effective synergistic approach to control intermolecular interaction and nanoscale bicontinuous phase separation for achieving high-performance ASM-OSCs.     

Impact of leakage current in germanium channel based DMDG TFET using drain-gate underlap technique

In this work, a dual metal (DM) double-gate (DG) Tunnel Field Effect Transistor (DMDG-TFET) with drain-gate underlap is proposed to overcome the challenges in conventional TFET. The ON-current (I_on), OFF-current (I_off), I_on/I_off ratio, subthreshold swing (SS) and ambipolar current (I_ambi) of the proposed device with drain underlap are investigated as gate length is scaled (L_GATE) down. The proposed device gives a better suppression in leakage current and low ambipolar current. The suppressed leakage current (I_off) and ambipolar current (I_ambi) are 9.49 × 10⁻¹⁴ A/µm and 1.95 × 10⁻¹² A/µm respectively for a gate length (L_GATE) of 36 nm and a channel length (L_Ch) of 50 nm for a supply voltage of 0.5 V. Excellent switching behavior is achieved when gate length (L_GATE) is 72% of the channel length (L_Ch). The proposed architecture is suitable for low power applications.     

Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET

We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al_0.83In_0.17N and narrowband GaN layers, along with high-k Al₂O₃ as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (V_t), I_on/I_off ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, I_on, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the I_off and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.     

Comparative assessment of III–V heterostructure and silicon underlap double gate MOSFETs

Comparative assessment of III?CV heterostructure and silicon underlap DG-MOSFETs, is done using 2D Sentaurus TCAD simulation. III?CV heterostructure device has narrow-band In_0.53Ga_0.47As and wide-band InP layers for body, and high-K gate dielectric. Density gradient model is used for simulation and interface traps are considered. Benchmarking of simulation results show that III?CV device provides higher on current, lesser delay, lower energy-delay product and lower DIBL than silicon device. However III?CV device has higher SS and lower I _on/I _off than silicon device. The results indicate that there is a need to optimize the I _on/I _off, SS and DIBL values for specific circuits.     

Enhanced Performance of I2‐Free Solid‐State Dye‐Sensitized Solar Cells with Conductive Polymer up to 6.8%

An iodine‐free solid‐state dye‐sensitized solar cell (ssDSSC) is reported here, with 6.8% energy conversion efficiency—one of the highest yet reported for N719 dye—as a result of enhanced light harvesting from the increased transmittance of an organized mesoporous TiO₂ interfacial layer and the good hole conductivity of the solid‐state‐polymerized material. The organized mesoporous TiO₂ (OM‐TiO₂) interfacial layer is prepared on large‐area substrates by a sol‐gel process, and is confirmed by scanning electron microscopy (SEM) and grazing incidence small‐angle X‐ray scattering (GISAXS). A 550‐nm‐thick OM‐TiO₂ film coated on fluorine‐doped tin oxide (FTO) glass is highly transparent, resulting in transmittance increases of 8 and 4% compared to those of the bare FTO and conventional compact TiO₂ film on FTO, respectively. The high cell performance is achieved through careful control of the electrode/hole transport material (HTM) and nanocrystalline TiO₂/conductive glass interfaces, which affect the interfacial resistance of the cell. Furthermore, the transparent OM‐TiO₂ film, with its high porosity and good connectivity, exhibits improved cell performance due to increased transmittance in the visible light region, decreased interfacial resistance ( Ω ), and enhanced electron lifetime ( τ ). The cell performance also depends on the conductivity of HTMs, which indicates that both highly conductive HTM and the transparent OM‐TiO₂ film interface are crucial for obtaining high‐energy conversion efficiencies in I₂‐free ssDSSCs.